C.M.P. PLANARIZATION FOR ULSI MULTILEVEL INTERCONNECTION
---SHORT COURSE---

Wednesday, February 10, 1999

The purpose of this SHORT COURSE is to provide an overview of current research activities for those issues impacting C.M.P. planarization used in the VLSI/ULSI multilevel interconnection technology. Another distinguished set of lecturers will participate in this SHORT COURSE which is a MUST for all engineers, managers and technicians working on VLSI multilevel interconnection. The registration includes coffee breaks, dinner and a visual booklet.

THIS COURSE HAS LIMITED ENROLLMENT, YOU ARE HIGHLY ENCOURAGED TO ADVANCE REGISTER EARLY.

 



I.     INTRODUCTORY REMARKS		   2:00 P.M.
		Thomas E. Wade
		Short Course Chairman

II.	ADVANCES IN CMP CONSUMABLES        2:05 P.M.
		Kathleen Perry
		Obsidian, Inc.; Fremont, CA

		       --Coffee Break--	   3:00 P.M.

III.	DIELECTRIC CMP PROCESSES           3:15 P.M.
		Dale Heatherington
		Sandia Nat'l Labs; Albuquerque, NM

IV.  METAL CMP PROCESSES                    4:10 P.M.
		Paul Feeney & Matthew Rutten
		IBM Microelectronics;  Essex Jct., VT

V.   CMP INTEGRATION ISSUES                 5:05 P.M.
		Nancy Heyley & 
		Joost Grillaert
	     	IMEC; Leuven, BELGIUM

		
                    Dinner	  6:05 P.M.
   		"SHALLOW TRENCH ISOLATION POLISHING"
		     Dr. Peter Burk
		     RODEL
                     Newark, Delaware

V.  ADVANCED CMP METROLOGY               7:05P.M.
		Gerry Collins & Arun Chatterjee
	     	KLA Tencor Corp.; San Jose, CA

VIII. CLOSING REMARKS   	   8:00 P.M.
		Thomas E. Wade

 

Short Course registration materials may be picked up at the Registration Desk from 12 - 2:00 P.M. on Wed., Feb. 10, 1999.

Additional registration - on a space available basis - will be conducted during this time also.

 

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