February 11 - 12, 1999

CMP-MIC CONFERENCE OBJECTIVES

To assemble researchers and technical support personnel from Industry, Universities and Government Laboratories from around the globe to address all current and future issues related to CHEMICAL-MECHANICAL POLISH PLANARIZATION as applied to on-chip ULSI Multi-level Interconnection applications.

OPENING SESSION - 9 A.M.,
Welcoming Remarks
Dr. Thomas E. Wade
General Chairman
University of South Florida

SESSION I -- 9:15 A.M.

KEYNOTE ADDRESS
" 300 mm/COPPER/LOW-k CONVERGENCE: TIMING, TRENDS & ISSUES"
Dr. Robert N. Castellano
THE INFORMATION NETWORK
New Tripoli, Pennsylvania

Coffee Break 9:45 - 10 A.M.

Chairman: Dr. Michael A. Fury
ALLIED SIGNAL

2.A "A New Fundamental Insight on Chemical Mechanical Polishing in IC Processes" by B. Zhao; ROCKWELL SEMI; Newport Beach, CA
Invited Paper (30 minute presentation)

2.B "In-Situ Monitoring of CMP Process Utilizing O-order Spectrometry" by Y. Ushio, T. Ueda, H. Nakahira, E. Matsukawa and M. Koyama; NIKON; Tokyo, JAPAN.

2.C "In-Water Film Thickness Measurements in CMP Process Control Applications" by D. Scheiner, Y. Cohen, A. Ravid, R. Kipper and M. Finarov; NOVA MEAS INSTRUMENTS; Rehovoth, ISRAEL.

2.D "The Influence of CMP Process Parameters on Slurry Transport" by J. Coppeta, R. Rogers, L.C. Racz; TUFTS UNIV.; Medford, MA; A. Philipossian; INTEL CORP; Santa Clara, CA; F.B. Kaufman; CABOT; Aurora, IL.

2.E "Dependence of Wafer Carrier Motor Current and Polish Pad Surface Temperature Signal on CMP Consumable Conditions and Ti/TiN Liner Deposition Parameters for Tungsten CMP Endpoint Detection" by G. Springer; SIEMENS; Dresden, GERMANY.(Session II continued)

2.F "Imaging Wafer-Scale Pressure Distribution for Chemical-Mechanical Polishing" by L.H. Wu and P.Y. Cheng; CHIAO-TUNG UNIV; Taiwan, R.O.C. and W.T. Tseng; CHENG-KUNG UNIV; Taiwan, R.O.C.

--- POSTER PAPERS ---

2.G "Particle Adhesion Force in CMP and Subsequent Cleaning Processes" by F. Zhang and A.A. Busnaina; CLARKSON UNIV; Potsdam, NY.

2.H "Study of Tungsten CMP Endpoint Window" by Z.H. Lin, H.W. Chiou, S.Y. Shih, L.H. Kuo, L.J. Chen and C. Hsia; ERSO/ITRI; Taiwan, R.O.C.

2.I "Atomic Force Profilometry for Characterization of Chemical Mechanical Planarization Process" by L.M. Ge and F.M. Serry; DIGITAL INST; Santa Barbara, CA; and T. Cunningham and D.J. Dawson; VEECO METROLOGY; Santa Barbara, CA.

2.J "Investigations of Polysilicon CMP to Apply in Sub-Quarter Micron DRAM Device" by N.H. Park, J.D. Koh, J.W. Park and J.J. Kim; LG SEMI; Cheongju, KOREA.

2.K "Novel Thin-Film Metrology for CMP Applications" by M. A. Joffe, H. Yeung, M. Fuchs and M.J. Banet; PHILIPS ANAL; Natick, MA.

2.L "Investigation of CMP Micro-Scratch in the Fabrication of Sub-Quarter Micron VLSI Circuits" by J. Huang, H.C. Chen, J.Y. Wu and W. Lur; UMC; Taiwan, R.O.C.

2.M "Comparison of Polisher Head Design Using Pattern TEOS Planarization Metrics" by H. Maeda; SUMITRONICS; San Luis Obispo, CA; and B. Kalenian, M. Lach and J. Curry; STRASBAUGH; San Luis Obispo, CA.

2.N "An Easy and Cost-Effective Method for Oxide CMP Process Control" by K. Tsai, M. Chang and T.Z. Huang; MOSEL VITELIC; Taiwan, R.O.C.

2.O "Optimization of Oxide and Metal Chemical Mechanical Polishing Using Extra Dummy Shot" by S.J. Kim, Y.W. Lee, S.Y. Kim and J.S. Choi; ANAM SEMI; Kyunggi-Do, KOREA.

2.P "Global Planarization CMP Using Conditioning Technology" by H.C. Chen, C.H. Chen, J.Y. Wu and W. Lur; UNITED MICRO CORP; Taiwan, R.O.C.

2.Q "A Discussion of Slurry Flow Rate Variation in CMP Delivery Systems" by C. Melcer; STRASBAUGH; San Luis Obispo, CA.

Box Lunches - 12:00 to 12:45 P.M.
Visit Industrial Exhibitors 12:45 - 1:30 PM

SESSION III - 1:30 - 3:30 P.M.
VLSI MULTILEVEL INTERCONNECTION
C.M.P. MODELING & SIMULATION

Chairman: Dr. Thomas Bibby
IPEC PLANAR
Tempe, Arizona

3.A "A CMP Model Combining Density and Time Dependencies" by T.H. Smith and D.Boning; MASS INST OF TECH; Cambridge, MA; S.J. Fang, G.B. Shinn and J.A. Stefani; TEXAS INSTRUMENTS; Dallas, TX.

3.B "The Use of a Semi-Empirical CMP Model for the Optimization of the STI Module" by J. Grillaert, M. Meuris, E. Vrancken, N. Heylen, K. Devriendt, W. Fyen and M. Heyns; IMEC; Leuven, BELGIUM.

3.C "Modeling and Discussions for STI CMP Process" by E. Tseng, M. Meng and S.C. Peng; UNITED SILICON INC; Taiwan, R.O.C.

3.D "Chip-Level CMP Modeling and Smart Dummy for HDP Film" by G.Y. Liu, R.F. Zhang and K. Hsu; INTERCON; Fremont, CA; L. Camilletti; ROCKWELL SEMI; Newport Beach, CA.

3.E "Implementing Large Area 3-D Pattern Erosion Simulation" by S.R. Runnels; SOUTHWEST RES INST; San Antonio, TX; I. Kim; SPEEDFAM; Chandler, AZ; and F. Miceli; LUCENT TECH; Murry Hill, NJ.

3.F "CMP Modelization: Planarization and Oxide Removal Simulation" by E. Perrin; S T MICRO; Crolles, FRANCE; and M. Rivoire; FRANCE TELECOM; Meylan, FRANCE.

--- POSTER PAPERS ---

3.G "The Effect of Polishing Pad Conditioning on the Planarization Capability of the Chemical Mechanical Polishing Process" by B. Mullany, G. Byrne; UNIV COLLEGE DUBLIN; Dublin, IRELAND and M. Power; INTEL IRELAND, Kildare, IRELAND.

3.H "Stacked Planarization Machine" by R.B. Clover; R.B. CLOVER ASSOC; Sunnyvale, CA; E. Vaaler; VAALER ENGR; Sunnyvale, CA; and E.R. Ward, Consultant, Sunnyvale, CA.

3.I "Polishing Selectivity Model for Tungsten CMP" by E. Tseng, M. Meng, S.C. Peng; UNITED SILICON; Taiwan, R.O.C.

3.J "Particle Dynamics in Grooves" by D. Bramono, J. Javidi, L. Racz and C. Rogers; TUFTS UNIV; Medford, MA; A. Philipossian; INTEL; Santa Clara, CA; and F.B. Kaufman; CABOT; Aurora, IL.

3.K "ANN Adaptive Multistep Polishing Control for Copper CMP" by C.T. Wang, W. Yueh; ASIA METAL; Taiwan, R.O.C.; W. Jeng, ASIA ICMP; Taiwan, R.O.C.

3.L "Hard Pad CMP or Soft Pad CMP - The Results of Pattern Density, Down Force, Step Height and Pad Compressibility" by E. Tseng, M. Meng and S.C. Peng; UNITED SILICON INC; Taiwan, R.O.C. >p>

Coffee Break 3:30 - 3:45 P.M.

SESSION IV - 3:45 - 5:05 P.M.
VLSI MULTILEVEL INTERCONNECTION C.M.P. CONDUCTOR PROCESSES

Chairman: Dr. Dale Hetherington
SANDIA NATIONAL LABS
Albuquerque, New Mexico

4.A "Influences of Fluid Boundary Layer Thickness on Tungsten Damascene CMP" by C. Lin, J. Wang and R. Ravikumar; SIEMENS MICRO; Hopewell Jct., NY; F. Jamin; IBM MICRO; Hopewell Jct., NY.

4.B "Evaluation of Cu CMP for Interconnects Using a New Slurry-Free Process" by M. Matsumoto, T. Sakamoto and A. Kamisawa; ROHM CO; Kyoto, JAPAN.

4.C "Electrical Characterization of Copper Chemical Mechanical Polishing" by T. Park, T. Tugbawa, D. Boning and J. Chung; M.I.T.; Cambridge, MA; and S. Hymes, R. Muralidhar, B. Wilks, K. Smekalin, G. Bersuker; SEMATECH; Austin, TX.

4.D "Copper / BCB Interconnects: Elimination of High Resistiv-ity Metallic Liners for Scaled Technologies" by J.M. Neirynck, R.J. Gutmann and S.P. Murarka; RENSSELAER POLYTECH; Troy, NY.

--- POSTER PAPERS ---

4.E "A Manufacturing Process for Tungsten Plug CMP on 200 mm Wafers Using a Speedfam Auriga Polisher and Cabot SSW 2000 Slurry" by J. Traut, J. Meyer and A. Gorby; HEWLETT PACKARD; Ft. Collins, CO; and T. Y. Yong, M. Monroe; HEWLETT PACKARD; Corvallis, OR.

4.F "Optimum Thickness of Barrier Layers for Damascene Process in High Density DRAM" by K. Tsai, C.H. Shu and T.Z. Huang; MOSEL VITELIC; Taiwan, R.O.C.

4.G "Oxide Erosion Characterization of a Tungsten CMP Process" by R. Lum, S. Mishra, F. Redeker, R. Lin and S. Nanjangud; APPLIED MATERIALS; Santa Clara, CA.

4.H "Comprehensive Revelation of Tungsten Chemical Mech-anical Polish" by L. H. Kuo, S.Y. Shih, H.W. Chiou, Z.H. Lin, L.J. Chen and C. Hsia; ERSO/ITRI; Taiwan, R.O.C.

4.I "Evaluation of Two Types of Tungsten Slurries for Dual Damascene" by B. Yen, F.Y. Shau, W.H. Chiang, C.S. Huang and C. Yi; PROMOS TECH; Taiwan, R.O.C.

Friday , February 12, 1999

SESSION V - 8:00 - 10:00 A.M.
VLSI MULTILEVEL INTERCONNECTION CMP CONSUMABLES & CLEANING

Chairman: Dr. Frank B. Kaufman
CABOT CORP
Aurora,Illinois

CMP CONSUMABLES

5.A "Development of Ta Slurry for 1:1:1 Cu:Ta:SiO2 Selectivity" by D. Mahulikar and A. Pasqualoni; OLIN METALS; New Haven, CT.

5.B "The Effect of Pad Structuring on CMP Performance" by K. Devriendt, E. Vrancken, M. Meuris, N. Heylen, W. Fyen, J. Grillaert and M.M. Heyns; IMEC; Leuven, BELGIUM; and A. Chung, and O. Hsu; FREUDENBERG NONWOVENS; Lowell, MA.

5.C "The Effect of Subpad Construction on Pattern Density Effects for Slurry-Free CMP" by D.P. Goetz; 3M CENTER; St. Paul, MN.

5.D "Step Height Reduction Characteristics of Fixed Abrasive Pad" by S. Kweon, J. Kang, B. Kwon, H.J. Kim, J.H. Lee, J.G. Lee and H. Hyun; HYUNDAI; Kyoungki, KOREA.

--- POSTER PAPERS ---

5.E "Particle Characteristics and Removal Rate in CMP Process" by R. Xu; BECKMAN COULTER; Miami, FL; C. Regulski; ACSI; Milpitas, CA; and J.E. Currie, CFT; Dover Plains, NY

5.F "A Robust, Manufacturable, Materials Technology: Novel Open-Celled, Polishing Pads for W CMP" by J. Beeler, S. Anjur, W. Downing, R. Sevilla, K. Newell, D. Smid, C. Dorsey, B. Cates, R. Hornbeck, R. Foster and F.B. Kaufman; CABOT; Aurora, IL.

5.G "Aging and Handling Evaluation of Tungsten CMP Slurry in Bulk Delivery System" by J.P. Bare and B. Johl; FSI INT'L; Hollister, CA.

5.H "CMP Slurry Filtration: Filter Plugging Mechanisms and Filter Lifetime Optimization" by Z. Lin, G. Vasiloupolos and P. Friedman; MILLIPORE; Bedford, MA.

CMP CLEANING PROCESSES

5.I "Particle Reduction by Optimization of Structure in CMP Carrier" by K. Ikenouchi, T. Murakami and Y. Miyoshi; MATSUSHITA; Toyama, JAPAN. 5.J "The Development of CMP Cleaning Process for New Inorganic and Organic Low k Dielectric Constant Materials" by L. Jiang, D. Hymes, M. Ravkin, J. Zhang and J. de Larios; ONTRAK SYS; Milpitas, CA.

---- POSTER PAPERS ---

5.K "Minimization of Defects in Oxide Post-CMP Cleaning" by Y. Epshteyn, D. Levedakis, G. Zhang, B. Groff, L. Von Gunter, T. Bui, J. Lee and A. Zutshi; IPEC; Phoenix, AZ.

5.L "Contact Post-CMP Cleaning of Thermal Oxide Wafers" by A.A. Busnaina, N. Moumen and J. Piboontum; CLARKSON UNIV; Potsdam, NY.

5.M "Defect Optimization for Polysilicon CMP" by M. Ravkin, J. Zhang, K. Mikhaylich; ONTRAK SYS; Milpitas, CA; D. Hetherington, D. Stein; SANDIA NAT'L LABS; Albuquerque, NM.

5.N "Water Conservation and Post CMP Cleaning: Are They Compatible?" by R. Small, Z. Chen, L. McGhee and M. Peterson; EKC TECH; Hayward, CA.

Coffee Break 10:00 - 10:15 A.M.

SESSION VI - 10:15 - 11:15 A.M.

VLSI MULTILEVEL INTERCONNECTION CMP SHALLOW TRENCH ISOLATION (STI)

Chairman: Dr. Duane Boning
MASS. INST. Of TECH. (MIT)
Cambridge, Massachussetts

6.A "Application of Ceria-Based High Selectivity Slurry to STI CMP for Sub-0.18 micron CMOS Technologies" by K.S. Choi, S.I. Lee, C.I. Kim, C.W. Nam, S.D. Kim and C.T. Kim; HYUNDAI; Kyoungki, KOREA.

6.B "A Production Proven Shallow Trench Isolation (STI) Solution Using Novel CMP Concepts" by R. R. Jin, J. David, T. Osterheld and F. Redeker; APPLIED MAT'L; Santa Clara, CA; and L. Liauzu; SGS-THOMSON; Crolles, FRANCE.

6.C "Improved STI CMP Technology for Micro-Scratch Issue" by M. Lin, C.Y. Chang; NAT'L CHIAO TUNG UNIV; Taiwan, R.O.C.; and D.C. Liao, B. Wang and A. Henderson; UNITED SEMI CORP; Taiwan, R.O.C.

--- POSTER PAPERS ---

6.D "The Effect of Feature Size and Counter Mask on Oxide CMP Removal Rate in Shallow Trench Isolation" by M. Jouty; S.T. MICRO; Crolles, FRANCE; M. Rivoire; FRANCE TELECOM; Meylan, FRANCE; and T. Detzel; RODEL EUROPE; Feldkirchen, GERMANY.

6.E "Characterization of Selective CMP, Dummy Pattern and Reverse Mask Approaches in STI Planarization Process" by P.H. Lo, T.C. Tsai, S. Lin, C.Y. Lee, E. Hsu, H.C. Wu, H.C. Chen and L.M. Liu; UTEK SEMI; Taiwan, R.O.C.

6.F "The Effect of Consumables in the Development of Advanced Shallow Trench Isolation (STI) CMP Processes" by J. Schlueter, I. Kim and F. Krupa; SPEEDFAM; Chandler, AZ.

6.G "Approach to One Step Shallow Trench Isolation CMP Process" by C.Y.C. Hsieh, C.T. Lee and J. Liang; WINBOND ELEC; Taiwan, R.O.C.

6.H "AFM Study of STI Topography During CMP With LPTEOS and HDP Gap-Filling" by F. Chen, S. Balakumar, J.Z. Zheng, C. Chern, B.B. Zhou and F.L. Chin; CHARTER SEMI; SINGAPORE.

6.I "The Effect of Belt Polishing on the Pattern Sensitivity in Shallow Trench Isolation (STI)" by C. Yi; PROMOS; Taiwan, R.O.C.; and M. Leach, F. Yang, I. Ali and P. Cheng; APLEX; Sunnyvale, CA.

6.J "Improvement of Defects in Shallow Trench Isolation (STI) Process" by D.Y. Kim, Y.S. Kim, H.S. Kim, S.P. Jung, S.Y. Kim and J.S. Choi; ANAM SEMI; Kyunggi, KOREA.

6.K "Evaluation of Different Types of CMP Polishers for One- Step STI Planarization" by L. Peng and C. Yi; PROMOS TECH; Taiwan, R.O.C.

SESSION VII - 11:15 A.M. - 12:30 P.M.

VLSI MULTILEVEL INTERCONNECTION
DEDICATED TIME FOR
C.M.P. POSTER PAPER, EXHIBITION VIEWING

CMP-MIC LUNCHEON - 12:30 - 2:00 P.M.

" GROWTH OF THE BUSINESS AND SCIENCE INFRASTRUCTURE FOR CMP "

Kathleen Perry
OBSIDIAN INC.
Fremont, California

SESSION VIII - 2:00 - 3:20 P.M.
VLSI MULTILEVEL INTERCONNECTION C.M.P. DIELECTRIC PROCESSES

Chairman: Dr. Ara Philipossian
INTEL CORP.
Santa Clara, CA.

8.A "Advanced Process Control in Dielectric Chemical Mechanical Polishing" by S.J. Fang and G.B. Shinn; TEXAS INSTRUMENTS; Dallas, TX. and T.H. Smith and D. Boning; MIT; Cambridge, MA.

8.B "Optimization of CMP Process for Inter Metal Dielectric Using HDP-CVD and PE-CVD Oxide Layer" by J.H. Kim, C.W. Nam, C.K. Oh, J.H. Ko, S.D. Kim and C.T. Kim; HYUNDAI; Kyungki, KOREA.

8.C "Selective Slurry in a Self-Stopping ILD CMP Process" by M. Oliver and S. Hosali; RODEL; Newark, DE; D.R. Evans; SHARP; Camas, WA; D. Hetherington, D. Stein and J. Stevens; SANDIA NATL LABS; Albuquerque, NM.

8.D "Optimization of CVD Oxide Thickness and CMP Planarization Efficiency for Inter-Metal Dielectric Process" by C.F. Lin and M.S. Feng; CHIAO-TUNG UNIV; Taiwan, R.O.C.; and W.T. Tseng; CHENG-KUNG UNIV; Taiwan, R.O.C.

--- POSTER PAPERS ---

8.E "Oxide Removal Rate Interactions Between Slurry, Pad, Downforce and Conditioning" by A.J. Clark, K.B. Witt and R.L. Rhoades; RODEL; Monroe, NC.

8.F "Optimize Oxide CMP Non-Uniformity on a Doughnut Shape Pad by Design of Experiment" by P.H. Lo, R.C. Lee, C.Y. Lee, E. Hsu, H.C. Chen,L.M. Liu; UTEK SEMI; Taiwan.

8.G "Chemical-Mechanical Planarization of BCB and SiLK Low - k Polymer Interlevel Dielectric in Copper Slurries" by C.L. Borst, W.N. Gill, R.J. Gutmann; RENSSELAER; Troy, NY.

8.H "Impact of Dummy Metal Structures on Post Oxide CMP Planarization" by C. Gillot and E. DeBacker; ALCATEL; and J. Grillaert and N. Heyley; IMEC; Leuven, BELGIUM; and J.M. Vaca, G. Blavier; KLA TENCOR; Meylan, FRANCE.

8.I "Effect of Linear Velocity and Pressure on Planarity" by D. A. Hansen; CYBEQ; San Jose, CA; H. Sun and R. Wall; PHILIPS SEMI; Albuquerque, NM. SESSION IX - 3:20 - 5:00 P.M.
VLSI MULTILEVEL INTERCONNECTION C.M.P. CONDUCTOR PROCESSES II

Chairman: Dr. Rahul Jairath
ON-TRAK SYSTEMS/LAM RES
Milpitas, California

9.A "Copper CMP and Process Control" by J. T. Pan, P. Li, K. Wijekoon, S. Tsai and F. Redeker; APPLIED MAT'L; Santa Clara, CA; and T. Park, T. Tugbawa and D. Boning; M.I.T.; Cambridge, MA.

9.B "The Role of Partlcle Hardness in the Chemical-Mechanical Polishing of Copper and Tungsten" by S. Ramarajan, M. Hariharaputhiran and S.V. Babu; CLARKSON UNIV; Potsdam, NY; and Y.S. Her, J.E. Prendergast; FERRO; Penn Yan, NY.

9.C "A Study of Pattern Effect on Tungsten Dishing and Oxide Erosion in Damascene CMP" by J.P. Boo, S.R. Hah, M.S. Han, S.Y. Tak, K.H. Kim and U.I. Chung; SAMSUNG; Yongin-City, KOREA.

9.D "Chemical-Mechanical Polishing of Aluminum and Copper Interconnects With Magnetic Liners and Oxide ILD" by B. Wang, R.J. Gutmann and T.P. Chow; RENSSELAER POLYTECH; Troy, NY.

9.E "Tungsten CMP Performance on a Linear Polisher" by D.J. Stein, D.L. Hetherington; SANDIA; Albuquerque, NM; and M. Ravkin, K. Mikaylich, ONTRAK SYS; Milpitas, CA.

--- POSTER PAPERS ---

9.F "Dual Damascene Al Integration for 0.25 micron SRAM Devices" by A.R. Sethuraman, A. Blosse, B. Koutny, U. Raghuram, C. Ford, S. Thekdi, J. Qiao, G. Lau, B. Parameshwaran, S. Geha, C. Goodenough, P. Krishnan, K. Kim, C.A. Seams; CYPRESS SEMI; San Jose, CA.

9.G "Al CMP Process: Effect of Process Parameters and Stability of Polishing Process" by H. Sieverding and G. Morsch; WOLTERS CMP SYS; Rendsburg, GERMANY.

9.H "Characterizing Buffing Step in Via/Contact and Damascene W-CMP" by T.C.Y. Yu, C.Y.C. Hsieh, C.F. Wang, H.Y.Ching, C.T. Lee and Y.C. Liang; WINBOND; Taiwan, R.O.C.

9.I "Methodology of Tungsten CMP Optimization: Over-Polish Effect on the Performance of Tungsten CMP" by W.L. Wang, T.H. Kuan, H.L. Wang and J. Dun; TSMC; Taiwan, R.O.C.; and W. Shen, K.Y. Wang, A. Chen and W. Pan; APPLIED MAT'L; Taiwan, R.O.C.

9.J "Yield Limiting Defect Mechanism by Dual Damascene Tungsten CMP" by C. Yi, F.Y. Shiue, B. Yen, C.S. Huang and R. Tang; PROMOS TECH; Taiwan, R.O.C.