DUMIC CONFERENCE OBJECTIVES

To assemble researchers and technical support personnel from Industry, Universities and Government Laboratories from around the globe to address all current and future issues related to DIELECTRICS for on-chip ULSI Multilevel Interconnection applications.

Monday, February 8, 1999

OPENING SESSION - 9 A.M.Welcoming Remarks
Dr. Thomas E. Wade
General Chairman
University of South Florida

SESSION I -- 9:15 A.M.
KEYNOTE ADDRESS

"HISTORY & FUTURE OF FLUOROCARBON CVD LOW k DIELECTRIC THIN FILMS"
Dr. Karen K. Gleason
MASSACHUSETTS INSTITUTE OF TECHNOLOGY
Cambridge, Massachusetts

Coffee Break 9:45 - 10 A.M

SESSION II - 10 A.M. - 12 Noon
VLSI MULTILEVEL INTERCONNECTION
ORGANIC DIELECTRICS, Part I

Chair: Dr. Carlye Case
ATT BELL LABS/ Lucent Tech.
Murry Hill, New Jersey

2.A "Structural, Optical and Electrical Properties of PECVD Fluorocarbon Films" by S. Gangopadhyay, X. Wang, H. Harri, G. Celebi, K. Bouldin, H. Temkin; TEXAS TECH UNIVERSITY; Lubbock, TX.; and M. Strathman, M. West; THIN FILM ANALYSIS; San Jose, CA.
Invited Paper (30 minute presentation).

2.B "Polybenzoxazole (PBO) Based Dielectrics for MCM and On-Chip Applications" by R. Sezi, A. Maltenberger, W. Radik, G. Schmid and A. Weber; SIEMENS AG; Erlanger, GERMANY; and K. Buschick; BERLIN TECH UNIV; Berlin, GERMANY.

2.C "Low-k Fluorinated Amorphous Carbon Dielectric for ULSI Multilevel Interconnection" by K. Endo; NEC CORP. Ibaraki, JAPAN.
Invited Paper (30 minute presentation).

2.D "Characterization of Low k Materials by Thermal Curing and Electron Beam Curing" by L. J. Chen, C. M. Wang and S. D. Lee; ERSO/ITRI; Taiwan, R.O.C.

2.E "SILK Evaluation As IMD With Copper Metallization" by J.C. Maisonobe, C. Lecornee, P. Noel; LETI GRESSI; Grenoble, FRANCE; C. Lacour, P. Motte, G. Passemard; ST MICRO; Grenoble, FRANCE; J. Torres; FRANCE TELECOM; Meylan, FRANCE.

Box Lunches - 12 Noon to 12:45 P.M.
Visit Industrial Exhibitors - 12:45 to 1:45 PM

Chairman: Dr. Robert D. Miller
I.B.M. ALMADER RES. CTR.
San Jose, California

3.A "Extendability of ICP High-Density Plasma CVD for Use as Intermetal Dielectric and Passivation Layers for 0.18 micron Technology" by J. Yota, A. Joshi; ROCKWELL SEMI; Newport Beach, CA.; J. Hander, D. Badt, L. Hoang, B. van Schravendijk and I.H. Park; NOVELLUS; San Jose, CA.
Invited Paper (30 minute presentation).

3.B "Characterization and Processing Considerations for Methyl-silsesquioxane Based Dielectrics" by W. Volksen, P. Furuta, C. Nguyen, D.Y. Yoon; R.D. Miller; IBM Almaden Res; San Jose, CA; K. P. Rodbell; IBM Watson Res; Yorktown, NY; and K. Linn; WASHINGTON STATE UNIV; Pullman, WA.

3.C "Characterization and Evaluation of HDPCVD FSG Production Capability" by Y.L. Wang, S.A. Wu, J. Dun; TSMC, Taiwan, R.O.C.; T.S. Yeh, S. Chen, S. Wang, R. Liao and A. Chen; APPLIED MAT'L TAIWAN, R.O.C.

3.D "PECVD Nitride of Low Hydrogen Content for Pre-Metal Dielectric Application in 0.25 micron Devices" by J.H. Lee, M. Wang, B. Thakur and J. Huang; APPLIED MATERIAL; Santa Clara, CA.; W. Li; LSI LOGIC; Santa Clara, CA.

3.E "High Density Plasma Phosphosilicate Glass Films for Advanced CMOS Technology" by D. Armbrust, J. Chapple-Sokol; L. Serianni, T. Chamberlin and K. Carlsen; IBM MICROELECTRONICS; Essex Jct., VT; B. Luneke; NOVELLUS SYS; Williston, VT.

Coffee Break 3:35 - 3:50 P.M.

Chairman: Dr. Rafael A. Mena
TEXAS INSTRUMENTS
Dallas, Texas

PART I - ANTI-REFLECTIVE COATING (ARC)

4.A "Improvement of Using Dielectric Anti-Reflective Coating (D-ARC) on DUV Photo CD Control for ULSI Applications" by G. Chao, P.Y. Lu, A. Ku, E. Mao, S. Chang and R. Tang; PROMOS TECH; Taiwan, R.O.C.

4.B "Advantages of Inorganic Anti-Reflective Coating PECVD SiOxNy for Sub-0.25 micron Gate Lithography and Etch Processes" by A. Kant, J. Yota and G. Talor; ROCKWELL SEMI; Newport Beach, CA. (Session IV continued)

4.C "A Novel Plasma Treatment Method to Improve DUV Photoresist Footing on Inorganic Anti-Reflective Layer (ARL)" by S. D. Lee, C.M. Wang, S.Y. Chou, L.J. Chen and C. Hsia; ERSO/ITRI; Taiwan, R.O.C.

PART II - DIELECTRIC RELIABILITY ISSUES I

4.D "Evolution of Defects in Borophosphosilicate Glass Films" by V.Y. Vassiliev, L. Chan; CHARTER SEMI; SINGAPORE; S.K. Tang and S. Mridha; NANYANG UNIV; SINGAPORE.

4.E "Effect of Plasma Enhanced CVD Oxide Composition on Metal Via Formation" by S.M. Chen and C.F. Lin; WINBOND; Taiwan, R.O.C.; W.T. Tseng; CHENG-KUNG UNIV; Taiwan, R.O.C.; M.S. Feng; CHIAO-TUNG UNIV; Taiwan, R.O.C.

SESSION V - 8:00 - 9:40 A.M.
VLSI MULTILEVEL INTERCONNECTION
RELIABILITY ISSUES II

Chairman:Dr. Philip J. Fleming
PHILIP J. FLEMING & ASSOC
Colorado Springs, CO.

5.A "Reduction of High Via Resistance by Via-Etch Process Modification" by C.D. Young, C.W. Cho, S.F. Chen and C.H. Chen; TSMC; Taiwan, R.O.C.

5.B "Water Absorption in Spin On Glass" by A. Burmeister, C. Carter and B. Tucker; SONY SEMI; San Antonio, TX.

5.C "Optimization of Plasma Clean Recipe for Sub-Atmospheric BPSG Chamber by Using New RF Endpoint Detector" by T. Huang, A. Ku, E. Mao, S. Chang and R. Tang; PROMOS TECH; Taiwan, R.O.C.

5.D "Tiny Nitride Residue Induced Gate Oxide Breakdown Failure" by Y.K. Hwang, T.T. Lee, T.C. Hsieh, H.Y. Yang, S.F. Chen and C.H. Chen; TSMC; Taiwan, R.O.C.

5.E "Application of Low k Dielectric Compatible Strippers/ Cleaners in Microlithography" by C.S. Hsu, D.C. Skee and G. Schwartzkopf; J. T. BAKER MICRO; Phillipsburg, NY.

Coffee Break 9:40 - 9:55 A.M.

Chairman: Dr. Douglas S. Armbrust
I.B.M. MICROELECTRONICS
Essex Junction, Vermont

6.A "Processing Methods to Fill High Aspect Ratio Gaps Without Premature Constriction" by R. Conti, L. Economikos and T. H. Ivers; IBM MICRO; Hopewell Jct, NY; A. Knorr; SIEMENS; Hopewell Jct., N.Y.; G. D. Papasouliotis; NOVELLUS; Hopewell Jct., N.Y.

6.B "Integration of HDP-FSG as ILD Material in Multilevel Interconnect Devices" by H. M'saad, M. Vellaikal, L. Zhang, Y. Wang, D. Witty, K. Rossman and F. Moghadam; APPLIED MATERIALS; Santa Clara, CA.

6.C "Porous Silica for Low Dielectric Application Development" by C.J. Wang, L.M. Chen, L.P. Li, H.H. Lu and T.Y. Lou; UNION CHEMICAL; Taiwan, R.O.C.

6.D "Shallow Trench Isolation Process Integration Challenges and Solutions" by J.P. Ellul, G. Menk and J. Foggiato; QUESTER TECH; Fremont, CA.; J. Boyd; STRASBAUGH; San Luis Obispo, CA.

6.E "Properties and Gap-Fill Capability of HDP-PSG Films for 0.18 micron Device Applications and Beyond" by V. Y. Vassiliev, C. Lin and J. Hui; CHARTER; SINGAPORE; D. Fung, J. Hsieh; NOVELLUS; San Jose, CA.

6.F "Advanced Pre-Metal Dielectric Films, Anneals and Integration of 0.15 micron Structures" by K. Kapkin, J. Sisson, S. Al-Lami and J.T. Pye; WATKINS JOHNSON; Scotts Valley, CA; B. Evans; GASONICS; San Jose, CA.

DUMIC LUNCHEON - 12:00 - 1:15 P.M.
" UNITY-k GAS DIELECTRICS FOR ULSI INTERCONNECTS"
Dr. Thomas E. Wade
UNIVERSITY OF SOUTH FLORIDA
Tampa, Florida

VISIT EXHIBITORS 1:15 - 1:50 P.M.

SESSION VII - 1:50 - 4:10 P.M.
VLSI MULTILEVEL INTERCONNECTION
ORGANIC DIELECTRICS II & SILSESQUIOXANE

Chairman: Dr. Arjun N. Saxena
INT'L SCIENCE CO.
Palo Alto, California

PART I - ORGANIC DIELECTRICS II

7.A "Characterization of Atomic Hydrogen Cross-Linked Parylene-N Produced by Jet Process" by L. Wang, J.F. McDonald, G.R. Yang, T.M. Lu and M. Tomozowa; RENSSELAER POLYTECH; Troy, NY; and B.L. Halpern, P. Komarenko, R.F. Graves and P.D. Fuqua; JET PROCESS; New Haven, CT.
(Invited Paper - 30 Minute Presentation)

7.B "Properties of Fluorinated Polyimide Films Prepared by Vapor Deposition for Multilevel Interconnection" by M. Iijima, S. Ukishima, M. Sato, Y. Takahashi, S. Sasaki, T. Matsuura and F. Yamamoto; ULVAC; Ibaraki, JAPAN.

7.C "AF4 (Alpha-Fluorinated Parylene) as the Low k Dielectric for Gap-Fill or Inlaid/Damascene Integration" by J.B. Easton; ALPHA METALS; Providence, R.I.

7.D "A Modified SOG Planarization Process in Passivation Scheme for Quarter Micron Process" by C. C. Tsan, Y. L. Wang, C. Y. Fu, and J. Dun; TSMC; Taiwan, R.O.C.; and T. S. Yeh, S. Wang and A. Chen; APPLIED MATERIAL; Taiwan, R.O.C.

PART II - SILSESQUIOXANE-BASED DIELECTRICS

7.E "E-Beam Curing Process of Low k Dielectrics for Unlanded Vias in 0.25 micron CMOS Technology" by D. Feiler, Q. Z. Liu and M. R. Brongo; ROCKWELL SEMI; Newport Beach, CA; and M. F. Ross, K. Livesay; ALLIED SIGNAL; San Diego, CA.

7.F "Thermal Cure Study of Inorganic Low k HSQ Spin-On Dielectric Film With High Resistance to Moisture Adsorption and Oxidation, and Good Thermal Stability" by J.C.M. Hui, E. Wong, Y. Xu and L. Charles; CHARTER SEMI; SINGAPORE; and H. Marshal and Y.F. Chow; INST OF MICRO; SINGAPORE.

7.G "The Effect of Ion-Implantation and E-Beam Cure on the Properties of Methyl Silsesquioxane Films" by C.Y. Wang, Z.X. Shen, S.L. Lim and A. Huan; NATL UNIV of SINGAPORE; and J. Z. Zheng and Y. Xu; CHARTER SEMI; SINGAPORE.

SESSION VIII - 4:10 - 5:30 P.M.
VLSI MULTILEVEL INTERCONNECTION
INORGANIC DIELECTRICS III

Chairman: Dr. Q. Z. Liu
ROCKWELL SEMICONDUCTOR
Newport Beach, California

8.A "An Integrated Simulation of the Plasma-Assisted Gate Oxide Nitridation" by V. Sukharev, S. Aronowitz, H. Puchner, V. Zubkov, J. Haywood and J. Kimball; LSI LOGIC; Santa Clara, CA.

8.B "A High Temperature, Low Pressure Ozone-TEOS Process for Shallow Trench Isolation" by S.M. Jang, Y.H. Chen, C.H. Yu and M.S. Liang; TSMC; Taiwan, R.O.C. and A. Chen; APPLIED MATERIAL TAIWAN; R.O.C.

8.C "Integration of HDP-CVD for Intermetal Dielectrics" by M. Alvarez, G. Sanchez, B. Sanchez, R. Bueno, E. Garcia and C. Mata; LUCENT TECH; Madrid, SPAIN

8.D "HDP-CVD PSG Process for PMD Applications" by M. Kwan, S.M. Cho, A. Collins, Z. Lin, K. Li, Z. Tan, P. Jennings, M. Barnes, J. Hamila, D. Tribula, K. Rossman and F. Moghadam; APPLIED MATERIALS; Santa Clara, CA.