“New Paradigms in Patterning & Process
Development to Extend Moore’s Law”
Kenneth MacWilliams; VP Applied Materials
Keynote Address - 1

“Recent Challenges & Solutions for Demanding
IC Interconnect Performance”
Axel Preusse; AMD Fellow, Dresden, Germany
Keynote Address 2

“Interconnect Scaling Challenges Beyond the
22 nm Node”
Sridhar Balakrishnan; Intel Corp.
Keynote Address - 3

 “Optimized Curing and CMP of Nanostructured
Ultra-Low-k Films”
Reinhold Dauskardt; Stanford University
VMIC Awards Luncheon (Thursday @ Noon)

“Impact of Interconnect Variations on Design”
Nagaraj NS; Texas Instruments
State-of-the-Art Seminar Luncheon

3-D IC Keynote Panel:
“3D IC Realization & Integration
For the 22 nm Technology Node
& Beyond”
J. Jay McMahon, SEMATECH – Moderator
Steve Koester, IBM
Jerry Bautista, INTEL
Robert Patti, TEZZARON SEMI
David Mountain, EXCEPTIONAL COMPUTING
Peter Ramm, FRAUNHOFER
Shinobu Fujita, TOSHIBA 

Two Sessions on 3-D IC’s and
Two Sessions on CMP Processing, and

 An Evening Panel Session on
‘25 Years of Interconnect’
Ron Gutmann, RPI - Moderator