TWENTY FIFTH INTERNATIONAL
VLSI/ULSI MULTILEVEL INTERCONNECTION
CONFERENCE

October 28 - 30, 2008

ADVANCE PROGRAM
 
Tuesday, October 28, 2008
OPENING SESSION --- 8:30 A.M.
 
Welcoming Remarks by the General Chairman
Dr. Thomas E. Wade
University of South Florida
  
SESSION I --- 8:45 A.M.
KEYNOTE ADDRESSES
 
“NEW PARADIGMS IN PATTERNING &
PROCESS DEVELOPMENT TO EXTEND
MOORE’S LAW”
by
Dr. Kenneth P. MacWilliams
Vice President & General Manager
Maydan Technology Center
APPLIED MATERIALS
Santa Clara, California
 
 
“RECENT CHALLENGES & SOLUTIONS
FOR DEMANDING IC INTERCONNECT
PERFORMANCE”
by
Dr. Axel Preusse
 AMD Fellow
AMD Fab 36
Dresden, Germany

“INTERCONNECT SCALING CHALLENGES
BEYOND THE 22 NM NODE”
by
Dr. Sridhar Balakrishnan
Mgr.: BEOL Integration for Future Tech.
INTEL CORPORATION
Santa Clara, California
Coffee Break 10:00 AM - 10:15 AM
 
 
SESSION II - 10:15 A.M. - 12:00 P.M.

VLSI MULTILEVEL INTERCONNECTION
KEYNOTE PANEL
 
“3-D IC REALIZATION &
INTEGRATION FOR THE 22 nm
TECHNOLOGY NODE AND
BEYOND”

PANEL MODERATOR
Dr. J. Jay McMahon
3D Integration Lead Engineer
SEMATECH 3D Interconnect Program

PANEL MEMBERS
 Steven J. Koester
IBM Watson Res. Ctr.
Yorktown Heights, New York

Jerry R. Bautista
INTEL CORPORATION
Santa Clara, California

Robert Patti
TEZZARON SEMI
Naperville, Illinois

David Mountain
CENTER for EXCEPTIONAL COMPUTING
Adelphi, Maryland

Peter Ramm
FRAUNHOFER IZM
Munich, Germany

Shinobu Fujita
TOSHIBA CORPORATION
Kawasaki, Japan
 
A brief Questions & Answer period will
follow formal presentations.
 
12:00 - 1:30 PM
VMIC 25TH ANNIVERSARY
RECOGNITION CEREMONIAL
LUNCHEON
 
Objective: To review the activities and accomplishment of VMIC since its
inception in 1983. In addition, to recognize those individuals who have delivered
past Keynote Addresses and/or the Awards Luncheon presentations. Some of those
present will provide brief comments. Past participants include: 

Dr. Arjun Saxena, AMI - 1984, 1986
Dr. John Moll, HP - 1984
Dr. Conrad Del Oca, VLSI Logic - 1985
Dr. James Meindl, Stanford U - 1985, 1987
Dr. Gordon Moore, Intel - 1986, 1993
Dr. Charles Sporck, National Semi - 1987
Dr. Paul Totta, IBM - 1988
Dr. Larry Sumney, SRC - 1988, 1992, 1996
Dr. Glen Madland, IC Engr - 1989
Dr. Thomas Seidel, SEMATECH - 1989, 1992
Dr. T. J. Rogers, Cypress Semi - 1990, 1993, 1996
Dr. Yoshio Nishi, HP/Stanford U - 1991, 1999, 2003
Dr. Bernd Hofflinger, IM-Germany - 1991
Dr. Dan Maydan, Applied Mat’l – 1994
Dr. Robert Burger, SRC - 1994
Dr. William Spencer, SEMATECH - 1995
Dr. Edbert Maynard, DARPA - 1995
Dr. Simon Sze, Hong Kong U - 1997
Dr. Christopher Case, Bell Labs - 1997
Dr. David Hodges, UC Berkeley - 1998
Dr. Robert Helms, TI - 1998
Dr. Hiroyoshi Komiya, Selete - 1999
Dr. Fabian Pease, Stanford U - 1999
Mr. Peter Singer, SI - 1999, 2006
Dr. Robert Castellano, Info Net - 2000
Dr. Shigeru Kobayashi, Selete - 2000
Dr. Jurgen Michel, MIT - 2001
Dr. Chi Shih Chang, Kulicke & Soffa - 2001
Dr. Gene Banucci, ATMI - 2002
Dr. Mayank Bulsara, Amberwave - 2002, 2004
Dr. Siva Sivaram, Matrix - 2003, 2004
Dr. Nobuyoshi Kobayashi, Selete - 2005
Dr. Takayasu Sakurai, U Tokyo - 2005
Dr. Sitaram Arkalgud, SEMATECH - 2005
Dr. Hiroshi Iwai, Tokyo Inst - 2005
Dr. Takeshi Nogami, Sony/IBM - 2005, 2007
Dr. Peng Bai, Intel - 2006
Dr. Kerry Bernstein, IBM - 2006
Dr. Roey Shaviv, Novellus - 2006
Dr. Susan Vitkavage, SEMATECH - 2006
Dr. Ahmed Busnaina, NE Univ - 2007
Dr. T.M. Mak, Intel - 2007
Drs. Nicholas Fuller & Tim Dalton, IBM – 2007
 
 
SESSION III - 1:30 - 3:30 P.M.
VLSI MULTILEVEL INTERCONNECTION
C.M.P. PROCESSES - Part 1
 
Chairman
Dr. Alexander Tregub
INTEL CORP
Santa Clara, California

 
3.A “Developing Contact Oxide CMP Process for 32 nm Technology Nodes” by J.H. Zhang, W. Kleemier, K. Barla and R. Sampson; ST MICROELECTRONICS; Hopewell Jct., N.Y.; R. Venigalla, D. C. Stoll, J. Wallner, C. Truong, X. Chen; IBM; Hopewell Jct., N.Y.; J. Sun; EBARA TECH; E. Fishkill, N.Y.; H. Zhuang; INFINEON; Hopewell Jct., N.Y.; C. Xiao; CHARTER SEMI; Hopewell Jct., N.Y. and J. E Koo, J.E. Park; SAMSUNG; Hopewell Jct., N.Y.
(Invited Paper)
 
3.B “Environmental Influence on Tungsten Plugs Quality During CMP Processing for Flash Memories” by Y. Shor, M. Mitlin, Y. Alon, D. Horvitz, N. Gurevich, E. Aboody and N. Amir; NUMONYX BV; Qiryat Gat, ISRAEL.

3.C “Materials Integration Challenges in Chemical Mechanical Polishing for 32 nm and Below” by Y. Wang, K. Xu, Y. Wang, I. Ali, M. Gage, S.H. Ko, S. Xia, W. Tu; APPLIED MATERIALS; Sunnyvale, CA.
(Invited Paper)

3.D “Pad Effect on Polish Behavior of Ceria Slurry in STI CMP” by C.Y. Ho, S.Y. Shih and S. Shih; NANYA TECH; Taiwan, R.O.C. 

3.E “A Novel Inspection Normal Illumination BF Advantage for Low-k CMP Applications Beyond the 45 nm Node” by C.Y. Cheng, S.N. Peng and S.C. Chen; ROHM & HAAS; Taiwan, R.O.C.; and B. Lalita, L. Jun, K. Satya, M. Koo, M. Ng and S. Chen; KLA-TENCOR; Milpitas, CA 

 3.F “Full Vision Endpoint for Dielectric CMP” by D.Bennett, J. Qian, S. Dhandapani, D. Benveqnu, J. Davis; APPLIED MATERIALS; Santa Clara, CA.    

 --- POSTER PAPERS ---

3.G “Effect of Guide Ring Surface Contact Area With Polishing Pad on Wafer Profile” by S. Kumar, C. K. Wei, A. K. Gupta, T. C. Soon and G. Dizon; CHARTERED SEMICONDUCTOR; SINGAPORE.

 3.H “Klebosol Slurry Compatible With New MagLev Day-Tank Technology” by B. Johl and H. Porter; ROHM & HAAS; Phoenix, AZ; and A.Quantik; LEVITRONIX; Waltham, MA. 

3.I “The Design Features of Ultimate Diamond Disks: W CMP With In-Situ Dressing of Metal Free Diamond Disks” by J.C. Sung, S. C. Hu, W. Huang, C.S. Chou, C. C. Chou and Y.L. Pai; KINIK; Taiwan, R.O.C.

Coffee Break 3:30 - 3:45 PM
 
SESSION IV - 3:45 - 5:30 P.M.
VLSI MULTILEVEL INTERCONNECTION
NOVEL PROCESSES

Chairman
Dr. Steven J. Koester
IBM WATSON RESEARCH CTR.
Yorktown Heights, New York 

4.A “Interconnect by Step and Flash Imprint Lithography” by C. G. Willson; UNIVERSITY Of TEXAS; Austin, TX.

4.B “Recent Advances in Silicon-Based Devices for Optical Interconnects” by L. Vivien, D. Marris-Morini, E. Cassan, G. Rasigade, J. Osmond, S. Laval; UNIVERSITY OF PARIS; Orsay, FRANCE; J-M Fedeli; CEA-LETI, Grenoble, FRANCE.
(Invited Paper)

4.C “Technology Options for Post-Copper, On-Chip Electrical Interconnects” by B. Geer; STATE UNIV Of NEW YORK; Albany, N.Y.
(Invited Paper) 

4.D “Can Integrated Photonics Solve the MPSoC Interconnect Issues?” by I. O’Connor, F. Mieryeville, F.Gaffiot; LYONS INST. Of NANOTECH; Lyon, FRANCE; A. Scandurra; ST MICROELECTRONICS; Catania, ITALY; and G. Nicolescu; POLYTECHNIC UNIV.; Montreal, CANADA.
(Invited Paper)

4.E "Implementation of Inverse Design Methodology for Device Integration" by J. St. Ville, A. Sidhwa and S. D.Rajan; ARMOR DESIGN; Phoenix, AZ.
(Invited Paper)

 
SESSION IV-A - 7:00 - 9:00 P.M.
Evening Panel Session
"IC Interconnect Technology and Design:
A Summary of the First 25 Years and a Projection
of the Future"

ORGANIZER/MODERATOR
Dr. Ronald Gutmann
RENSSELAER POLYTECHNIC INST.

OBJECTIVE

This panel will review the on-chip interconnect developments of the last 25 years as well as project future needs/developments. WE NEED YOUR INPUT/ EXPERTISE in identifying both short term (i.e., 5 - 10 years) and long term (i.e., 25 years) goals & challenges for specific areas of interconnect development (i.e., CMP, metal/dielectrics, novel structures, etc.). (A Summary Report will be formulated for distribution to interested parties, including the SEMI Interconnect Roadmap Committee.)

PANEL
Dr. Arjun N. Saxena
International Science Co.; Palo Alto, CA
"Interconnect Process Techniques/Development"

Dr. Timothy Cale
Arizona State University; Tempe, AZ
"Interconnect Processing Model & Simulations"

Dr. Michael A. Fury
InterCrossIP Management; San Francisco, CA
"Interconnect Entrepreneurial Opportunities"

Dr. Robert Geer
State University of New York at Albany
"Post Copper - Low k Alternatives"
 
 
Wednesday, October 29, 2008
SESSION V - 8:00 - 10:35 A.M.
VLSI MULTILEVEL INTERCONNECTION
3-D  I.C. PROCESSES - Part I
(An Invited Session)
 
Chairman
Dr. John F. McDonald
RENSSELAER POLYTECHNIC INST.
Troy, New York

 5.A “Electrical Modeling & Characterization of Through-Silicon Vias (TSVs) for 3-D Integrated Circuits” by I. Savidis; UNIV. Of ROCHESTER; Rochester, N.Y.; S.M. Alam; EVERSPIN TECH; Austin, TX; A. Jain, S. Pozder and R.E. Jones; FREESCALE SEMI; Austin, TX; R. Chatterjee; GEORGIA INST. Of TECH; Atlanta, GA.

5.B “Test Results for a Fabricated 3 Tier 3-D FDSOI SRAM” by J. F. McDonald, R.P. Kraft, P. Belemjian, O. Erdogan, P. Jacobs, A. Zia, A. Gutin; RENSSELAER POLYTECH. INST.; Troy, N.Y.

5.C “Architecture Implications of 3-D Integration” by M. Ignatowski; IBM WATSON RES. CTR.; Yorktown Heights, N.Y.

5.D “3-D Integration Technology for Realizing Super Chip” by T. Tanaka, T. Fukushima, M. Koyanagi; TOHOKU UNIV.; Sendai, JAPAN.

5.E “A Wafer-Level 3-D Integration Technology Platform Using Damascene Patterned Metal/Adhesion Hybrid Bonding” by J.J. McMahon and G. Smith; SEMATECH; Albany, N.Y.; R.J. Gutmann, J.Q. Lu; RENSSELAER POLYTECH INST; Troy, N.Y.
(Invited Paper)

5.F “3-D System-In-A-Stack Technology” by V. Ozguz and J. Yamaguchi; IRVINE SENSORS; Costa Meas, CA.

 
--- POSTER PAPERS ---

5.G “Diamond Heat Spreader Thermal Analysis for 3D Memory Over Processor Chip Stacks and Effect on TSV Reliability” by J. F. McDonald, R.P. Kraft, P. Belemjian, O. Erdogan, P. Jacobs, A. Zia, A. Gutin and R. Clarke; RENSSELAER POLYTECH. INST; Troy, N.Y.

5.H “Hybrid Copper/ILD Bonding for 3D Stacking of IC’s” by C. S. Tan; NAT’L TECHNOLOGY UNIV; SINGAPORE.
(Invited Paper)

Coffee Break 10:35 - 10:45 A.M.

 
SESSION VI - 10:45 A.M. - 12:15 P.M.
VLSI MULTILEVEL INTERCONNECTION
DIELECTRIC, RELIABILITY
& LITHOGRAPHY PROCESSES
 
Chairman
Dr. Willi Volksen
IBM ALMADEN RES. CTR.
San Jose, California

DIELECTRIC PROCESSES

6.A “An Air-Corridor Interconnect Structure” by J. Park and C. Hu; UNIVERSITY Of CALIFORNIA; Berkeley, CA 6.B “A Highly Reliable Ultralow Dielectric Constant Porous Silica Film With Acetonylacetone Incorporation” by F.T. Huang, W.L. Yang, L. M. Lin, S.Y. Huang and C.A. Wang; FENG CHIA UNIV; Taiwan, R.O.C.

--- POST PAPER ---

6.C “Dielectric Nanostructure Deposition by Focused Particle Beams; A Comparative Study” by H.D. Wanzenboeck, G. Hochleitner, M. Fischer, E. Bertagnolli; VIENNA UNIV. Of TECHNOLOGY; Vienna, AUSTRIA.

 RELIABILITY

 6.D “CoWP Metal Cap Technology Ready for High Volume Manufacturing?” by M. Nopper; AMD; Dresden, GERMANY.
(Invited Paper)

6.E  “Selective Copper-Sulfide Passivation Capping for Copper Interconnects” by U. Cohen; UC CONSULTING; Palo Alto, CA.

 -- POSTER PAPER --

6.F “Double Metal-Insulator-Metal Capacitor Breakdown Voltage Improvement by Stacked Film & Process Optimization in High-Voltage Process” by K. Wang, V. Wu, C. Huang, J. Huang, K. Yang, K.I. Huang, T. S. Wu and K. C. Su; U.M.C.; Taiwan, R.O.C.

6.G  “Threshold Voltage Shifts Due to Sweep Beam Control Stumble in Medium Current Implanter” by S.Y. Chiou, J.Y. Ma, J. Chen; PROMOS TECH; Taiwan, R.O.C.

LITHOGRAPHY

6.H “Interconnect Variability Analysis for Double Patterning Lithography” by R.O. Topaloglu; ADVANCED MICRO DEVICES; Sunnyvale, CA.
(Invited Paper)
 
6.I  “Short, Mid and Long Term Outlook for Lithographic Patterning” by J.G. Hartley; STATE UNIV. Of NEW YORK, Albany, N.Y.
(Invited Paper)

[Wednesday Lunch on Your Own
Not Provided by Conference]


SESSION VII - 1:00 - 2:00 P.M.
VLSI MULTILEVEL INTERCONNECTION
POSTER PAPER / EXHIBITION
DEDICATED VIEWING TIME


SESSION VIII - 2:00 - 5:45 P.M.
VLSI MULTILEVEL INTERCONNECTION
CARBON NANOTUBES &
PROCESSING METHODS


Chairman
Dr. Cary Y. Yang
SANTA CLARA UNIVERSITY
Santa Clara, California


CARBON NANOTUBE/NANOFIBER
DEVELOPMENTS

8.A “Post-CMOS Graphene and Carbon Nanotube Device Integration” by C. Borst; STATE UNIV. Of NEW YORK; Albany, N.Y.
(Invited Paper)

8.B “Estimation of an RLC Granularity Metric for a CNT-Bundle Interconnect Stack” by D. Ni, T.M. Lam and Y.L. LeCoz; RENSSELAER POLYTECH. INST; Troy, N.Y.; and A. Naeemi, J.D. Meindl; GEORGIA INST. Of TECHNOLOGY; Atlanta, GA.

8.C “Effect of Current Stressing on Horizontal Carbon Nanofiber Interconnects” by T. Yamada, T. Saito, D. Fabris and C.Y. Yang; SANTA CLARA UNIV.; Santa Clara, CA.
(Invited Paper)

PROCESSING METHODS

 8.D “Design Aware RIE Process Optimization for Via/Contact Pattern Transfer” by V. Sukharev, A. Markosian, V. Kudryavtsev, L.Manukyan, N. Khachatryan, A. Kteyan, H. Lazaryan, H. Hovsepyan, J-H. Choy; MENTOR GRAPHICS; San Jose, CA.
(Invited Paper)
 
8.E “Atomic Layer Deposition for Nanoscale Contact Applications” by H.B.R. Lee and H. Kim; POHANG UNIV.; Gyungbuk, KOREA
(Invited Paper)

8.F “VCM-Based Design of Key Components for Plasma Deposition Chambers to Eliminate Induced Defects During Processing” by A. Sidhwa, J. St. Ville and S. Rajan; ARMOR DESIGN; Phoenix, AZ.

 
Thursday, October 30, 2008
SESSION IX - 8:30 - 10:30 A.M.
VLSI MULTILEVEL INTERCONNECTION
3-D  I.C. PROCESSES - Part II
(An Invited Session)
 
Chairman
Dr. John F. McDonald
RENSSELAER POLYTECH. INST.
Troy, New York

 9.A “Smart Power Delivery Using Three-Dimensional IC Technology With Arrays of Monolithic DC-DC Point-of-Load (PoL) Converters” by R. J. Gutmann and J. Sun; RENSSELAER POLYTECH. INST.; Troy, N.Y.

9.B “Folding Tape Method: Novel Layout Method for 3D Circuit to Effectively Decrease Interconnect Delay” by S. Fujita, K. Abe, K.Nomura, S. Yasuda and T. Tanmoto; TOSHIBA; Kawasaki, JAPAN.
 
9.C “Application and Design Automation for 3D Integrated Circuits” by P. D. Franzon, W. R. Davis, M. B. Steer, H. Hao, S. Lipa, S. Luniya, C. Mineo, J. Oh, A. Sule. T. Thorolfsson; NORTH CAROLINA STATE UNIV; Raleigh, N.C. L. McIlrath; R3 LOGIC, Cambridge, MA; and K. Obermiller, T. Doxsee; PTC; Cambridge, MA.
 
9.D “Quantitative Studies of Impact of 3D IC Design on Repeater Usage” by J.Cong, C. Liu and G. Luo; UNIVERSITY Of CALIFORNIA, Los Angeles, CA.
 
9.E “New Developments in Wafer Bonding for 3D Integration” by T. Matthias; EV GROUP; Tempe, AZ; and V. Dragoi, S. Pargfrieder and P. Lindner; EV GROUP; Florian/Inn, AUSTRIA.

9.F “3D Wafer Bonding With a Silicon Germanium HBT BiCMOS Wafer for Compact Fast Light Modulator for Photonic Interconnect” by J. F. McDonald, R. P. Kraft, J.R. Guo, P.Belemjian, O. Erdogan, P. Jacobs, A. Zia, Y. Yim, M. Chu, J.W. Kim, J.Q. Lu, S. Deng and R. Huang; RENSSELAER POLYTECH. INST.; Troy, N.Y.

 Break 10:30 - 10:45 A.M.
 
 
SESSION X - 10:45 A.M. - 12:00 P.M.
VLSI MULTILEVEL INTERCONNECTION
METALS PROCESSES &
MODELLING/SIMULATION
 
Chairman
Dr. Ardy Sidhwa
ARMOR DESIGN
Phoenix, Arizona

 
METAL PROCESSES

10.A “Copper Oxide and Copper Thin Films Grown by ALD for Seed Layer Applications” by T. Waechtler, CHEMNITZ UNIVERSITY; Chemnitz, GERMANY; and S. E. Schulz; FRAUNHOFER RES. INST; Chemnitz, GERMANY.10.B “Advanced Electroless Deposition in Metallization Processes” by H.C. Koo, M.C. Kang, T. Lim, K.J. Park and J.J. Kim; SEOUL NAT’L UNIVERSITY; Seoul, KOREA.
(Invited Paper)

MODELLING & SIMULATIONS

10.C “Optimizing Global Interconnect Process Variations in Statistical Static Timing Analysis” by E. A. Foreman and P. A. Habitz; IBM MICRO-ELECTRONICS; Essex Junction, VT; and M.C. Cheng; CLARKSON UNIVERSITY;Potsdam, N.Y. 

10.D "PMD CMP Modeling: Another Step Towards a Full-Stack CMP Simulation Framework" by B. Lee, E. Drege, K. Ichikawa, and A. Gower-Hall; CADENCE DESIGN SYS; San Jose, CA.
(Invited Paper)

10.E “Modeling and Validating Gigahertz-Level Time Domain Multi-Port Sub-65nm Transmission Line Parameters” by JF Huang, HY Cho, CY Chang, S. Liu; TSMC; Taiwan, R.O.C.; K.J. Chang; Nat’l Tsing Hua Univ.; Taiwan, R.O.C.
(Invited Paper)

--- POSTER PAPERS --- 

10.F “A Sum-Over-Paths Algorithm for Third-Order Impulse-Response Moment Extraction Within RC IC Interconnects” by E. A. Wojcik, T.M. Lam, D. Ni and Y.L. LeCoz; RENSSELAER POLYTECH. INST.; Troy, N.Y.

 
SESSION XI - 1:30 - 3:30 P.M.
VLSI MULTILEVEL INTERCONNECTION
CMP PROCESSES - Part II
 
Chairman
Dr. Alexander Tregub
INTEL CORP.
Santa Clara, California

11.A “Evolution of Surface Profile During Barrier Polishing With Slurries of Different Selectivities” by H.Chang, K. Yang, T. Lee and W. Chu; BASF ELECTRONIC MAT’L; Taiwan, R.O.C.
 
11.B “Polysilicon Chemical Mechanical Planarization Process Development Using New Slurry” by S. Balakumar and Z. Leory; INST. Of MICRO-ELECTRONICS; SINGAPORE; and E. Chew; CABOT MICRO.; SINGAPORE.
 
11.C “Particle Improvement by Minimizing Wafer Contact With Machine Hardware” by S. Kumar, T.C. Soon, C. K. Wei, A. K. Gupta and G. Dizon; CHARTERED SEMICONDUCTOR; SINGAPORE.
 
11.D “Controlled DI Water Gasification System for Advanced Semiconductor Cleaning Processes” by A. Xia, K. Niermeyer, R. Mollica and G. Conner; ENTEGRIS; Billerica, MA.
 
11.E “Development of a Cu Polish Process for the Speedfam Auriga C” by C. Brannon, C. Nauert and M. Wedlake; SPANSION; Austin, TX.

--- POSTER PAPERS ---

11.F “Polycrystalline Diamond Shaving Dresser: The Ultimate Diamond Disk for CMP Pad Conditioning” by J.C. Sung, C.S. Chou, C. C. Chou, Y.L Pai and S. C. Hu; KINIK; Taiwan, R.O.C.; and Y.T. Chen; NAT’L DEFENSE UNIV; Taiwan, R.O.C.; and M. Sung; ADVANCED DIAMOND SOLN; San Francisco, CA.
 
11.G “Comparison of Zone Control Capability Between Two Kinds of Zone Heads” by S. Huang, C.M. Liao, S.Y. Shih, S. Shih; NANYA TECH; Taiwan, R.O.C.

11.H “Tungsten CMP With In-Situ Dressing of Metal Free Diamond Disks” by S.C. Hu, W. Huang, C. S. Chou, C.C. Chou, Y.L. Pai and J.C. Sung; KINIK; Taiwan, R.O.C.

 
******************************************
NOTICE TO AUTHORS OF POSTER PAPERS

Plan to put ALL posters for ALL SESSIONS up on Tuesday, October 28, before 9:30 am at the location designated (Check at Conference Registration Desk). Poster boards will be provided as indicated in author kits. Be available AT YOUR POSTER to answer questions during Session VII (from 1:00 - 2:15 pm on Wednesday). Plan to remove your poster on Thursday afternoon from 2 - 3 pm, October 30.

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