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VLSI MULTILEVEL INTERCONNECTION STATE-OF-THE-ART SEMINAR Monday, September 24, 2007 This year’s state-of-the-art SEMINAR will address those issues associated with current fundamental developments in advancing VLSI/ULSI multilevel interconnection towards greater functionality, density and speed. It will include a review and discussion of those primary topical areas which impact todays multilevel interconnection event as well as project future direction for this critical industry. A distinguished set of lecturers will participate in this SEMINAR, which is a MUST for all engineers, managers and technicians working on VLSI/ULSI multilevel interconnection. The registration fee includes coffee breaks, luncheon and a visuals booklet. THIS COURSE HAS LIMITED ENROLLMENT. YOU ARE ENCOURAGED TO ADVANCE REGISTER EARLY. TOPICAL COVERAGE I. INTRODUCTORY REMARKS - 9:00 A.M.
II. C.M.P.:
Coffee Break - 10:00 A.M. III. C.N.T.:
IV. LITHOGRAPHY:
Seminar Luncheon 12:00 P.M.
“SILICON PHOTONICS: Dr. Mario Paniccia INTEL CORPORATION San Clara, California
V. LOW - k DIELECTRICS:
VI. AIR - GAPS:
Coffee Break - 2:45 P.M. VII. 3-D INTEGRATED CIRCUITS:
VIII. HIGH-k DIELECTRICS:
IX. CLOSING REMARKS - 4:30 P.M.
Short Course registration materials may be picked up at the Registration Desk from 7 - 10 A.M. on Monday, September 24, 2007. Additional at-door registrations will be conducted during this time as well. |
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