TWENTY FOURTH INTERNATIONAL

TWENTY FOURTH INTERNATIONAL

VLSI/ULSI MULTILEVEL INTERCONNECTION

CONFERENCE

September 25 - 27, 2007

ADVANCE PROGRAM

Tuesday, September 25, 2007

OPENING SESSION --- 8:30 A.M.

Welcoming Remarks by the General Chairman

Dr. Thomas E. Wade

University of South Florida

SESSION I --- 8:45 A.M.

KEYNOTE ADDRESSES

“PARADIGM SHIFT IN INTERCONNECT TECHNOLOGY:

DIRECT ASSEMBLY OF SINGLE-WALLED CARBON

NANOTUBE AND NANOPARTICLE INTERCONNECTS”

Dr. Ahmed Busnaina

Director

NSF NANOSCALE SCIENCE & ENG’R CENTER FOR

HIGH-RATE NANOMANUFACTURING

Northeastern University

Boston, Massachusetts

—

“CHALLENGES WITH HIGHER

DEGREE OF INTEGRATION”

Dr. T. M. Mak

Manager, Technology Manufacturing

INTEL CORPORATION

Santa Clara, California

—

“SILICON PROCESSING TECHNOLOGIES

IN ADJACENT SPACES:

APPLICATIONS BEYOND INFORMATION TECHNOLOGY”

Drs. Nicholas Fuller & Timothy Dalton

I.B.M. WATSON RESEARCH CTR.

Yorktown Heights, New York

SESSION II - 10:15 A.M. - 12:30 P.M.

VLSI MULTILEVEL INTERCONNECTION

KEYNOTE PANEL

“RESEARCH CHALLENGES IN 3-D IC

REALIZATION/INTEGRATION”

(Objective: Identify those research challenges

associated with realizing & integrating 3-D IC processes

in a manufacturing environment.)

PANEL MODERATOR

Dr. John F. McDonald

RENSSELAER POLYTECHNIC INST.

PANEL MEMBERS

Michael Fritze

DARPA

Washington, DC

Robert Patti

TEZZARON SEMI

Naperville, Illinois

Fabian Pease

STANFORD UNIVERSITY

Stanford, California

Volkan Ozguz

IRVINE SENSORS CORP.

Costa Mesa, California

Rajit Manohar

CORNELL UNIVERSITY

Ithaca, New York

Dorota Temple

R.T.I. INTERNATIONAL

Research Triangle Park, NC

Paul Franzon
NORTH CAROLINA STATE UNIV.
Raleigh, NC

A brief Questions & Answer period

will follow formal presentations.

Box Lunches 12:30 - 1:30 P.M.

SESSION III - 1:30 - 3:50 P.M.

VLSI MULTILEVEL INTERCONNECTION

C.M.P. PROCESSES - Part 1

Chairman: Dr. Alexander Tregub

INTEL CORP.

Santa Clara, California

3.A “Line Yield Improvement by Novel In-Line Detect Development for Tungsten CMP Defects” by D. Horvitz, Y. Alon, O. Shinder, V. Viclov, A. Rozen-blat, M. Weinstock, M. Horev, M. Mitlin and Y. Shor; INTEL CORP; Kiruat, ISRAEL.
(Invited Paper)

3.B “Ruthenium Barrier Films as an Alternative for Tantalum” by C. Burkhard, Y. Li; CLARKSON UNIV.; Potsdam, N.Y.; and J. Chamberlain; RESEARCH WAFERS; Hickory, N.C.

3.C “Multi-Scale Physical CMP Simulation Framework for Design for Manufacturing & Yield (DMY)” by T. Yoshida; YNT; Yamaguchi, JAPAN.

3.D “Copper CMP Removal Rate Predictions Using Alumina Agglomerate Size Distributions” by R. Ihnfeldt and J.B. Talbot; UNIV. Of CALIFORNIA - SAN DIEGO; La Jolla, CA.

3.E “High Productivity Combinatorial Analysis of Post Copper CMP Cleans: The Effect of Queue Time” by J. Barnes, P. Zhang; ATMI; Dansbury, CT; and A. Duong, Z. Fresco, C.I. Lang and N. Rutherford; INTERMOLECULAR; San Jose, CA.

3.F “Performance Aware CMP Fill Pattern Optimization” by A.B. Kahng; UNIV. Of CALIF. SAN DIEGO; La Jolla, CA; and R. O. Topaloglu; AMD; Sunnyvale, CA. and U.C. SAN DIEGO.
(Invited Paper)

3.G “CMP Corrosion Behavior of Electroplated Copper in H2O2-Based Slurry” by J.C. Chen, M.W. Chen, J.Y. Lai, Y.D. Fan, Y.Y. Wang; T.S.M.C.; Taiwan, R.O.C.; and J.Y. Lin, C.C. Wan; NAT’L TSING-HWA UNIV.; Taiwan, R.O.C.
(Invited Paper)

--- POSTER PAPERS—

3.H “The Fabrication of Ideal Diamond Disk by Casting Diamond Film on Silicon Wafer” by J.C. Sung, M.C. Kan, H.K. Chang; KINIK; Taiwan, R.O.C.; and Y.T. Chen; NAT’L DEFENSE UNIV; Taiwan, R.O.C.; and M. Sung; ADV. DIAMOND SOLN; San Francisco, CA.

3.I “WBUFF Center Ring Type Foggy Defect Improvement for EBARA F-REX200" by W.C. Liaw, S.Y. Yang, W.Y. Lin, H.H. Hsiaoa, Y.F. Wang; Hsinchu City; Taiwan, R.O.C.

3.J “Zero Defectivity Performance Through Pad Design and Material Optimization of Novel Pad Platform” by R. Carpio and F. Tolic; ATDF; Austin, TX; and S. Hymes, R. Bajaj; SEMIQUEST; San Jose, CA

3.K “Application of a Simple Density Dependent CMP Model to Predict Oxide Polish Time in a Production Environment” by M. Hossain, M. Hoang, N. Nguyen; B. Hameih, T. Gandy, A. Sidhwa and B.Y. Mao; ST MICROELECTRONICS; Phoenix, AZ.

Coffee Break 3:50 - 4:00 PM

SESSION IV - 4:00 - 5:45 P.M.

VLSI MULTILEVEL INTERCONNECTION

DIELECTRICS & CONDUCTORS

Chairman: Dr. Willi Volksen

IBM ALMADEN RES. CTR.

San Jose, California

DIELECTRIC SYSTEMS

4.A “Superior Mechanical Properties of Dense and Porous Organic/Inorganic Hybrid Thin Films” by W. Volksen, G. Dubois, T. Magbitang, R.D. Miller; IBM ALMADEN RES. CTR.; San Jose, CA; and D.M. Gage, R.H. Dauskardt; STANFORD UNIV; Stanford, CA.
(Invited Paper)

4.B “High k Dielectric Process Control by Means of AR-XPS, AFM and STEM-EELS” by G. Conti, Y. Uritsky, C.C. Wang, C. Lazik, S. Hung, T.E.Sato P.M. Liu; APPLIED MATERIALS; Santa Clara, CA. (Invited Paper)

CONDUCTOR SYSTEMS

4.C “The Development of Ruthenium-Based Alloys for Direct Plating Copper Barrier Applications” by S. Kumar, D. Greenslit and E. Eisenbraun; UNIV. Of ALBANY - SUNY; Albany, N.Y.
(Invited Paper)

4.D “Application of CVD - W Diffusion Barrier Layers to Dual Damascene Copper Contacts” by K. Wang, A. Cuthbertson, J.C. Yeoh, R. Herberholz, S. Colledge, H.P. Coulson, D. Watson and G. Braithwaite; ATMEL N. TYNESIDE; Newcastle Upon Tyne, UNITED KINGDOM and A.B. Horsfall, A.G. O’Neill; NEWCASTLE UNIV; UNITED KINGDOM.

4.E “Advancement in Metallization Barriers” by G.T.Stauf, T. Chen, C. Xu, J.I. Arno, T.H. Baum and J.F. Roeder; ATMI; Dansbury, CT.
(Invited Paper)

4.F “Golden Parameter Ratio Application in Tungsten Via Fill and Interconnect Metal Recipe Development” by J. H. Zhang and J. Radja; ST MICROELECTRONICS; Carrollton, TX

--- POSTER PAPERS---

4.G “Generation and Resolution of Dense Defect in Boron-Doped Oxide Film” by C.Y. Wang, S.W.Yang, C.K. Kao, C.M. Kuo and A. Ku; PROMOS TECH; Taiwan, R.O.C.

Wednesday, September 26, 2007

Invited Session

SESSION V - 8:00 - 10:35 A.M.

VLSI MULTILEVEL INTERCONNECTION

3-D I.C. PROCESSES

(Session Organized by Jack McDonald, RPI)

Chairman: Dr. Cary Y. Yang

SANTA CLARA UNIVERSITY

Santa Clara, California

5.A “Wafer Level 3-D Integration” by R. Yu, IBM WATSON RES. LAB; Yorktown Heights, N.Y.

(Invited Paper)

5.B “Circuit Design for 3-D Integration” by N. Checka, R. Berger, B.Tyrrell, and C. Keast; M.I.T. LINCOLN LABS; Cambridge, MA; and A. Chandrakasan, R. Reif; M.I.T.; Cambridge, MA
(Invited Paper)

5.C “3-D Architecture Modeling and Exploration” by J. Cong, E. Kursun, Y. Liu, and G. Reinman; UNIV. Of CALIFORNIA; Los Angeles, CA; Y. Ma; TSINGHUA UNIV.; CHINA.
(Invited Paper)

5.D “Precise Wafer Thinning Using the Mathematics of the Radon Transform for 3-D Chip-Stacking” by J.F. McDonald, R.P. Kraft, P. Belemjian, P. Jacob, A. Zia, M. Chu, J.W. Kim, S. Suhag, R. Daminski, N. LiCausi and J.Q. Lu; RENSSELAER POLYTECH. INST.; Troy, N.Y.

5.E “CAD for 3-D Circuits: Solutions and Challenges” by S.S. Sapatnekar; UNIV. Of MINNESOTA; Minneapolis, MN. (Invited Paper)

5.F “Progress in Copper-Based Wafer Bonding” by C.S. Tan; NAT’L TECHNOLOGY UNIV; SINGAPORE; and A. Chandrakasan, R. Reif: M.I.T.; Cambridge, MA.
(Invited Paper)

5.G “A 3D FDSOI 1-T Floating Body Capacitance (FBC) DRAM Suitable for Processor Integration” by A. Zia, P. Jacobs, J.F. McDonald, R.P. Kraft, P. Belemjian; RENSSELAER POLYTECH. INST.; Troy, N.Y.

5.H “Designing FIFO Buffers Using 3-D IC Technology” by A.M. Sule and W.R. Davis; NORTH CAROLINA STATE UNIV.; Raleigh, N.C.

Invited Session

SESSION VI - 10:45 A.M. - 12:15 P.M.

VLSI MULTILEVEL INTERCONNECTION

NOVEL & AIR GAP

PROCESSES

Chairman: Dr. Paul Kohl

GEORGIA INST. Of TECH.

Atlanta, Georgia

NOVEL PROCESSES

6.A “Architectures, Functions and Integration of Photonic Interconnection in CMOS” by M. Beals, J. Michel and L.C. Kimerling; M.I.T.; Cambridge, MA
(Invited Paper)

6.B “Charged Particle Beam Induced Nano-Machin-ing for Advanced Mask Repair and Integrated Circuit Modification” by R. Livengood, T. Liang and Y. Greenzweig; INTEL CORP; Santa Clara, CA
(Invited Paper)

AIR GAP PROCESSES

6.C “Fabrication of Intra-Level Extended Air-Gaps Using the Harder Sacrificial Polymer Placeholder for Ultra Low-k Dielectrics” by S. Park, S.A.B. Allen and P.A. Kohl; GEORGIA INST. Of TECH; Atlanta, GA.; and J. Krotine; PROMERUS; Brecksville, OH

6.D “Air Gap Integration for Edge Interconnect Technologies” by F. Gaillard; CEA-LETI-Minatec; Grenoble, FRANCE; and V. Arnal; ST MICRO-ELECTRONICS; Crolles, FRANCE.
(Invited Paper)

6.E “High-Performance, Air-Cladded Transmission Lines on FR-4 and BT Substrates” by T.J. Spencer and P.A. Kohl; GEORGIA INST. Of TECH.; Atlanta, GA

[Wednesday Lunch on Your Own

Not Provided by Conference]

SESSION VII - 1:00 - 2:00 P.M.

VLSI MULTILEVEL INTERCONNECTION

POSTER PAPER / EXHIBITION

DEDICATED VIEWING TIME

Invited Session

SESSION VIII - 2:00 - 5:30 P.M.

VLSI MULTILEVEL INTERCONNECTION

CARBON NANOTUBES &

MODEL/SIMULATIONS

Chairman: Dr. Barbara Wacker

NANOCONDUCTION INC.

Sunnyvale, California

CARBON

NANOTUBE/NANOFIBER

DEVELOPMENTS

(Session Organized by B. Wacker)

8.A “Towards Integration of Carbon Nanotubes With CMOS” by K. Teo, Y. Zhang, X. Wang, S. Haque, N. Rupesinghe, F.Udrea, W. Milne; CAMBRIDGE UNIV; Cambridge, UNITED KINGDOM.

8.B “Multilevel Interconnects Using Vertically Aligned Carbon Nanofibers” by J.Li; KANSAS STATE UNIV; Manhattan, KS; A.M. Cassell, Q. Ngo, M. Meyyappan; NASA AMES RES. CTR.; Moffett Field, CA; H. Kitsuki, M. Suzuki, K. Gleason, C.Y. Yang; SANTA CLARA UNIV; Santa Clara, CA.

8.C “Copper Foil / Carbon Nanotube Array Thermal Interface Materials Used for CPU Burn-In” by B. A. Cola, T.S. Fisher; PURDUE UNIV; Lafayette, IN; and M.R. Maschmann, C. Henry; INTEL CORP; Chandler, AZ.

8.D “Carbon Nanofibers Under High-Current Stress for Interconnect Applications” by H. Kitsuki, K. Gleason, P. Wilhite, M. Suzuki, Q. Ngo and C.Y. Yang; SANTA CLARA UNIV; Santa Clara, CA.; and A.M. Cassell, J. Li; NASA AMES RES. CTR; Moffett Field, CA.

8.E “Heating Effect Investigation of Individual Carbon Nanotube for Interconnect Applications” by Y. Zhang; NANOCONDUCTION: Sunnyvale, CA

8.F “Carbon Nanotubes as Thermal Interface Materials” by B.A. Cruden; NASA AMES RES. CTR; Moffett Field, CA.

MODEL & SIMULATION

OF I.C. PROCESSES

8.G “An Atomic View of Atomic Layer Deposition” by C. Musgrave and A. Mukhopadhyay; STANFORD UNIV; Stanford, CA.
(Invited Paper)

8.H “Via Chamfering Modeling for Improved MIM Capacitance Silicon Correlation” by R.O. Topaloglu, ADVANCED MICRO DEVICES; Sunnyvale, CA.

8.I “Interconnect Parasitics Sensitivity for Modeling and Analysis of Process Variation in Nanometer Technology” by Z. Ren, D. Petranovic and J. Falbo; MENTOR GRAPHICS; San Jose, CA.
(Invited Paper)

8.J “A Sum-Over-Paths Impulse-Response Moment-Extraction Algorithm for IC Interconnect Networks: Verification, Coupled RLCM Lines” by Y.L. LeCoz and D. Krishna; RENSSELAER POLYTECH. INST.; Troy, N.Y.; and D.M. Petranovic; MENTOR GRAPHICS; Wilsonville, OR.

8.K “DFM Integrated Chip Scale CMP and Electro-plating Simulator” by N. Strecker, Y. Granik; MENTOR GRAPHICS; San Jose, CA.

8.L “More Than Modeling: The Use of CMP Modeling for Design Optimization” by B. Lee, E. Drege, W. Luo, R. Pyke and L. Song; CADENCE SYSTEMS; San Jose, CA.
(Invited Paper)

Thursday, September 27, 2007

SESSION IX - 8:00 - 10:00 A.M.

VLSI MULTILEVEL INTERCONNECTION

RELIABILITY ISSUES

Chairman: Dr. Ardy Sidhwa

ST MICROELECTRONICS

Phoenix, Arizona

9.A “Post-Etch Residue Removal for Advanced Copper / Low-k Devices Utilizing a Metal Hardmask Integration Scheme” by H. Cui and S. Kirk; DUPONT EKC; Hayward, CA
(Invited Paper)

9.B “Electromigration Performance Improvement by PVD Process Optimization for Advanced Aluminum Interconnect” by C. Huang, V. Wu, C.P. Kuan, B. Ju, J.W.Liang, T. Hsieh, H.S. Shih, K.P. Chang and K.C. Su; UMC; Taiwan, R.O.C.

9.C “Role of Titanium-Boron Interaction in Silicon / Metal Delamination Mechanism” by S. Kim, M.D. Gruenhagen, J. Pierce, J. Murphy and T.P. Welch; FAIRCHILD SEMI; West Jordan, UT.

9.D “Reduction of Yield Impacted Shallow Trench Isolation (STI) Micro-Scratches” by T.H. Lim; B.L. Koh, S. Mahapatra; APPLIED MATERIALS South East Asia; K.L. Chan; B.H. Chan and C.W. Lee; ST MICROELECTRONICS; SINGAPORE.

9.E “Copper / Low-k BEOL Process Integration of 90 nm NOR Flash and Their Effect on Cell Characteristics, RC Delay and Prevention of Copper Diffusion” by S. Joo, S. Kim, C. Shim, J. Hong, S. Kim, J. Han, K. Kim; DONGBU HITEK; Chungbuk, KOREA.

9.F “Elimination of Consumption Streak Yield Loss Pattern By Using Custon Teflon Shield Cassette for Wet Acid Processing Tools” by J. Tamim, R. Constantine, L. Hall, J. Darr, R. Nelson, R. Sanchez, R. Korb, G. Spawn, T. Gandy, Y. Dao, R. Sampson, A. Sidhwa and B.Y. Mao; ST MICROELECTRONICS; Phoenix, AZ.

--- POSTER PAPERS ---

9.G “Implementation of Silicon Etch to Improve the Dice Pick and Place Process at the Assembly Processing Step” by G. Kuhel, C. Petronis, J. Darr, N. Slaney, A. Sidhwa and B.Y. Mao; ST MICROELECTRONICS; Phoenix, AZ.

9.H “Superior Alternatives for BEOL / FEOL Cleans in 45 nm and 32 nm Device Generations” by C.P. Hsu, E. Sheen, K. Dailey, K. Trovalli, W. Cady and J. Covington; J. T. BAKER MICRO; Phillipsburg, N.J.

9.I “Improvement of Via Instability Due to a Embed-ded Moisture” by K. Ritari, R. Piotrowski, J. Darr, T. Gandy, B. Hameih, A. Sidhwa, R. Sampson and B.Y. Mao; ST MICROELECTRONICS; Phoenix, AZ.

9.J “Multiple Failure Analysis Applications Using Strasbaugh nOvation” by E. Beaton and L. Yao; STRASBAUGH; San Luis Obispo. CA.

9.K “Reduction of the Wafer Backside Chips and Crack in the Backend of the Line Wafer Manufacturing Process” by G. Kuhel, R. Pierce, C. Petronis, R. Farrell, J. Darr, N. Slaney, A. Sidhwa and B.Y. Mao; ST MICROELECTRONICS; Phoenix, AZ

9.L “Influence of Low Temperature Barrier Nitride Film on Transistor Characteristics for Advanced DRAM” by D. Hamza, C.Wang, P. Lin, T. Kao, C. Kuo and A. Ku; PROMOS TECH; Taiwan, R.O.C.

9.M “Aluminum Interconnect Defectivity Caused by Loss of PVD Chamber Vacuum Integrity” by J. Degraffenreid, X. Breurec, M. Datema, B. Hamieh, T. Gandy,A. Sidhwa and B.Y. Mao; ST MICRO-ELECTRONICS; Phoenix, AZ.

Break 10:00 - 10:15 A.M.

SESSION X - 10:15 A.M. - 12:30 P.M.

VLSI MULTILEVEL INTERCONNECTION

Chairman: Dr. Ronald Gutmann

RENSSELAER POLYTECH INST

Troy, New York

CMP PROCESSES - Part II

10.A “Investigation of the Roles of Anionic Poly-electrolytes in Copper CMP” by Y. Li, C. Wang; CLARKSON UNIV; Potsdam, N.Y.; and X. Chen, Z. Wu and Y. Li; SUN YAT-SEN UNIV; Guangdong, CHINA

10.B “Defect Reduction in Tungsten CMP Through Optimization of Wafer and Pad Rotational Speed at Water Polishing Step” by T.C. Soon, G. Dizon, A. Kumar and C.K. Wei; CHARTERED SEMI. MFG.; SINGAPORE

10.C “Raising Throughput; Slashing Variable Cost - A Theory of Constraints Examination of Applied Materials Mirra-Mesa Copper Polisher” by M. Wedlake; SPANSION; Austin, TX; and B. Hollingsworth, G. Bourgeois and J.W. Hunt; UNIV. Of TEXAS; Austin, TX.

(Invited Paper)

10.D “Unique SmartPad Technique for CMP End-Point Applications” by L. Yao, A. Dalrymple, B. Sennett, R. Treur, M. Kirkpatrick and B. Kalenian; STRASBAUGH; San Luis Obispo, CA

10.E “Chemical Mechanical Planarization of Wide Band Gap Materials for Optoelectronics and Power Electronics Applications” by R.K. Singh; UNIV. Of FLORIDA; Gainesville, FL.
(Invited Paper)

10.F “Rapid Screening of Copper CMP Slurries, ECMP Electrolytes and Pads” by Y. Li; CLARKSON UNIV; Potsdam, N.Y.; Y. Li; ST. LAWRENCE NANOTECHNOLOGY; Potsdam, N.Y.; and F. Zhu; RISHANG TECH; Tianjin, CHINA

10.G “Process Optimization With 300mm Oxide/STI Pad” by J.Y. Kim, D. Huang and M. Lube; PRAXAIR; Dansbury, CT; and R. Caramto; STATE UNIV. Of NEW YORK, Albany, N.Y.

--- POSTER PAPERS ---

10.H “Novel High Purity, pH Stable Colloidal Slurry” by S. Holland, W. Mullee, R. Small and K. Holland; TECHCET; Genoa, NV.

10.I “Yield Enhancement and Cost Reduction by Advanced Tungsten Slurry Implementation” by J.D. Jeong, S.Y. Kim, H.S. Kim, J.K. Lee, H.P. Kim, H.W. Ha, Y.S. Kim, J.H. Go, and D. Li; DONGBU-HITEK; Gyeonggi, KOREA; and J.B. Park; CABOT MICROELECTONICS, Aurora, IL.

10.J “PCD Dressers for Making CMP Pad Conditioners” by H. Ishizuka, E. Nishizawa; TOMEI DIA INT’L; Tokyo, JAPAN; J.C. Sung; KINIK; Taiwan, R.O.C.; and M. Sung; ADV. DIAMOND SOLUTIONS; San Francisco, CA

10.K “New Pad Structure of Memory Devices to Solve the Package Issue in Sub-45 nm Technology” by C. Shim, M.W. Kim, J.H. Hong, S.G. Kim, J.W. Han, K.H. Kim; DONGBU HITEK; Chungbuk, KOREA.

10.L “Pump Induced Particle Agglomeration During CMP of Metal and Dielectrics” by F.C. Chang and R. Singh; UNIV. Of FLORIDA; Gainesville, FL.

2007 VMIC AWARDS LUNCHEON

Thursday, September 27; 12:30 - 2:00 P.M.

“3-D System Integration, Challenges

And Opportunities”

Dr. Eric Beyne

IMEC

Leuven, Belgium

“‘Interconnect Society’ Within the IEEE –

Long Overdue”

Dr. Thomas E. Wade

VMIC GENERAL CHAIRMAN

University of South Florida

Tampa, Florida

SESSION XI - 2:15 - 3:30 P.M.

VLSI MULTILEVEL INTERCONNECTION

INTERCONNECT PROCESSES

Chairman: Dr. Yoshio Li

CLARKSON UNIVERSITY

Potsdam, New York

11.A “Study of Alignment on DRAM BEOL Process Integration” by K.W. Chung, A.H. Liu and C.K.Lin; NANYA TECH; Taiwan, R.O.C.; and N. Schittenhelm, U. Malkoc; QIMONDA; Dresden, GERMANY.

11.B “Development of a New-Post Etch Photoresist Stripper for Copper BEOL Process” by B. Du, E. Kneer and P.H. Townsend; FUJIFILM; Mesa, AZ.

11.C “Development of New PMD Structure to Overcome Gap-Fill Process Limit Beyond 90 nm NOR Flash Device” by H. Lim, J. Park, S. Kim, J. Han, K. Kim; DONBU HITEK; Chungbuk, KOREA.

******************************************

NOTICE TO AUTHORS OF POSTER PAPERS

Plan to put ALL posters for ALL SESSIONS up on Tuesday, September 26, before 9:30 am at the location designated (Check at Conference Registration Desk). Poster boards will be provided as indicated in author kits. Be available AT YOUR POSTER to answer questions during Session VII (from 1:00 - 2:15 pm on Wednesday). Plan to remove your poster on Thursday afternoon from 2 - 3 pm, September 28.

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