2007 CMP-MIC ELEVENTH INTERNATIONAL

TWELFTH INTERNATIONAL

C.M.P. PLANARIZATION

FOR ULSI MULTILEVEL INTERCONNECTION

CONFERENCE

March 6 – 8, 2007

Tuesday, March 6, 2007

OPENING SESSION - 8:30 A.M.

Welcoming Remarks

Dr. Thomas E. Wade, Gen. Chmn.

University of South Florida

SESSION I -- 8:30 A.M.

KEYNOTE ADDRESS

“CMP’S TRANSITION TO THE NEXT GENERATION WAFER”

In addition to enhanced wafer size, new technologies (i.e. Intel’s high-k/metal gate stacks) and new materials (i.e., barriers, etc.) generate many new challenges for future CMP processes.

PANEL MODERATOR

Peter Singer

Editor-in-Chief

Semiconductor International

SEMICONDUCTOR IND. PANEL

Michael Goldstein, Intel, Santa Clara, CA

Janos Farkas, Freescale, Crolles, FRANCE

Peter Thieme, Qimonda, Dresden, GERMANY

Robert Rhoades, Entrepix, Tempe, AZ

A brief Question & Answer period

will follow formal presentations.

Coffee Break 10:00 - 10:15 AM

SESSION II - 10:15 A.M. - 12:00 P.M.

VLSI MULTILEVEL INTERCONNECTION

CMP CONSUMABLES - SLURRY Part I

Chairman: Dr. Mansour Moinpour

INTEL CORP.

Santa Clara, California

2.A “Copper Slurry Design for Copper / p-Low k Interconnects” by Y. Tateyama, G. Minamihaba, D. Fukushima, T. Nishioka and H. Yano; TOSHIBA; Yokohama, JAPAN.
Invited Paper

2.B “Electrochemical Analysis of Copper CMP Slurries” by C. Poutasse and J. Huo; FUJIMI CORP; Tualatin, OR

2.C “Barrier CMP Slurry: Self-Stopping on the Ultra Low - k Materials” by P. Monnoyer, F. Sebai and J.Farkas; FREESCALE SEMI; Grenoble, FRANCE.
Invited Paper

2.D “Optimization of Abrasives and Chemistry in CMP Slurries for Defect Reduction” by F. Coder, A. Meyers, R. McConnell, J. Siddiqui, S. Usmani, S. Shrauti, G. Zhang and A. Zutshi; DUPONT NANOMAT’L; Hayward, CA
Invited Paper

2.E “Chemical Modifications of CMP Slurries to Address Thick Copper Applications” by C. Perrot, Y.Loquet, P. Bouillon, B.Iteprat, N. Burgnies and M. Vincent; ST MICROELECTRONICS; Crolles, FRANCE

--- POSTER PAPERS —

2.F “Role of Slurry Chemistry on Pump Induced Particle Agglomeration During CMP of Copper/ Low-k Dielectrics” by F.C. Chang, S. Tanawade and R. Singh; UNIV Of FLORIDA; Gainesville, FL.

2.G “Research and Application of Polysilicon Slurry for Chemical Mechanical Polishing in 60 nm Devices” by J.C. Yang, J.H. Kim, J.D. Kim and S.H. Yoo; SAMSUNG ELECTRONICS; Yoingin-City, KOREA.

2.H “Precision Flow Control and Enhanced Filter Lifetime in Magnetically Levitated Pump Based CMP Slurry Delivery System” by R.K. Singh, K. Anderson and B. Bjorneberg; ENTEGRIS; Billerica, MA; and J. Hahn and L. Bauck; LEVITRONIX; Gmbh; Waltham, MA.

2.I “CMP Slurry Processing and Filtration: Opportunities for Point of Use Filtration” by M. Serafin, N. Nelson and R. Olmsted; IMATION; Oakdale,

2.J “Low Defectivity Ceria Particle Manufacturing” by C. Zedwick, B. Her, B. Santora and K. Erskine: FERRO ELECTRONICS; Penn Yan, N.Y.

Box Lunches - 12:00 - 1:00 P.M.

Visit Industrial Exhibition/Poster Presentations

SESSION III - 1:00 - 3:20 P.M.

VLSI MULTILEVEL INTERCONNECTION

CMP RELIABILITY ISSUES

Chairman: Dr. Janos Farkas

FREESCALE SEMI.

Crolles, France

3.A “Influence From Slurry Distribution on Corrosion During Tantalum Polish” by M.Dicks and J. Plagmann; INFINEON AG; Regensburg, GERMANY
Invited Paper

3.B “Investigation of Chemical Diffusion in Porous Ultra Low-k Material During CMP and Post-CMP Cleaning Steps” by A. Castex and J. Farkas; FREESCALE; Crolles, FRANCE; S. Gall; CEA-LETI; Grenoble, FRANCE; M. Rivoire; ST MICROELECTRONICS;Crolles, FRANCE.

3.C “Application of Bevel Polishing to Defect Reduction in FEOL Process Flow” by A. Shigeta, Y. Tateyama, D. Fukushima, T. Nishioka and H. Yano; TOSHIBA CORP; Yokohama, JAPAN.

3.D “Investigation of the Roles of Halides in Copper CMP” by Y. Li, K. Cheemalapati; CLARKSON UNIV;Potsdam, N.Y.; and X. Chen, Z. Wu and Y. Li; SUN YAN-SEN UNIV; Guangzhou, CHINA.

3.E “Using Scatterometry for Erosion Measurements of the Copper CMP Process” by S. Rosenthal; TOWER SEMI; Migdal Haemek, ISRAEL.

3.F “65 nm Yield Detector Caused by M1 Filament Shorts and Solution” by Y.C. Ee, S.K. Tan, C.S.Chee, J.B. Tan, B.C. Zhang, Y.K. Siew, P.K. Tan, F.Zhang, K.H.Lai, M.S. Chettiar, X.B. Wang, T. Fu and L.C. Hsia; CHARTER SEMI; SINGAPORE; and A. Inani, N. Akiya, L. Yuan and A. Agarwal; PDF SOLUTIONS; San Jose, CA.

3.G “How to Recognize When a Good CMP Process Has Gone Bad” by R. Rhoades; ENTREPIX; Tempe, AZ
Invited Paper

--- POSTER PAPERS ---

3.H “Study of Wafer Center CP Loss by Scrubber Jet Clean After WCMP Process” by D. Ke, S. Chung, H. Liao, K.J. Chen, C.K. Chung and M. Yu; UNITED MICRO CORP; Taiwan, R.O.C.

3.I “Study on Post CMP Cleaning on Ultra Low-k Dielectric for Direct Barrier CMP Development in L45 IC Fabrication” by H.N. Tai, J.Y. Fang, C.L. Hsu, C.H. Chen, C.C. Huang; UNITED MICRO CORP; Taiwan, R.O.C.

Coffee Break 3:20 - 3:35 PM

SESSION IV - 3:35 - 5:00 P.M.

VLSI MULTILEVEL INTERCONNECTION

C.M.P. CONSUMABLES - PADS

Chairman: Dr. Peter Thieme

QIMONDA SEMI

Dresden, Germany

4.A “Characterization of CMP Consumables: Correlation Between Material Properties and CMP Performance” by T. Bramblett, S. Narayanan and A. Tregub; INTEL CORP; Santa Clara, CA.

4.B “Measurement of CMP Pad Texture Contact, Deformation and Flow Resistance: Advances in Pad Design and Process Predictability” by G. P. Muldowney; C.L. Elmufdi, B. Jiang and R. Palaparthi; ROHM HAAS; Newark, DE.
Invited Paper

4.C “Pad Property - Dominated Lubrication Behavior of CMP” by D. Ng and H. Liang; TEXAS A & M UNIV; College Station, TX.
Invited Paper

--- POSTER PAPERS ---

4.D “Length Scale Specific Performance Improvements Via Novel Pad Platform Architecture” by R. Carpio and F.Tolic; ATDF; Austin, TX; and S. Hymes, R. Bajaj; SEMIQUEST; San Jose, CA.

Wednesday, March 7, 2007

SESSION V - 9:00 A.M. - 12:00 P.M.

VLSI MULTILEVEL INTERCONNECTION

CMP DIELECTRIC PROCESSES &

CMP APPLICATIONS

Chairman Dr. Peter Burke

ON SEMICONDUCTOR

Phoenix, Arizona

CMP DIELECTRIC PROCESSES

5.A “Challenges of STI CMP on DRAM Device Scaling” by C-H. Kuo, K.W. Chung and C.K. Lin;NANYA TECH;Taiwan, R.O.C.; F. Meyer, H. Heidemeyer, P. Faustmann; QIMONDA; Dresden, GERMANY.

5.B “In-Die Topography Monitoring for STI CMP Processing With AFM Depth Metrology” by M. Caldwell; FREESCALE SEMI; Austin, TX; and T. Bao; VEECO INSTRUMENTS; Santa Barbara, CA.

5.C “Characterization of Advanced Shallow Trench Isolation (STI) CMP Processes and Consumables” by C. Burkhard and Y. Li; CLARKSON UNIV; Potsdam, CA.

--- POSTER PAPERS ---

5.D “Process Development of a Hybrid Fixed Abrasive for Direct SACVD STI CMP” by T.C. Tsai, C.Lu, K.G. Yang, N. Chen,C.H. Chen, C. Y. Lee, C.C. Huang and S.F. Tzou; UNITED MICRO CORP.; Taiwan, R.O.C.

CMP APPLICATIONS

5.E “CMP in NOR Flash Memory: Challenges and Development” by L. Zhang et al; INTEL CORP; Santa Clara, CA.
Invited Paper

5.F “Copper and Barrier CMP for Magnetic Random Access Memory (MRAM) Devices” by J. Zabasajja; FREESCALE SEMI; Chandler, AZ.
Invited Paper

5.G “Developing Poly Silicon Chemical Mechanical Polish Process for MEMs” by J. H. Zhang and J. Radja; ST MICROELECTRONICS; Carrollton, TX.

5.H “Development of a Production Worthy Fixed Abrasive Process for Logic Applications at 45 nm Technology Node and Beyond” by T.C. Tsai, C. Lu, C.H. Chen, K. Wu, C.C. Huang and S. F. Tzou; UNTED MICROELECTRONICS CORP; Taiwan, R.O.C.

5.I “Rapid and Gentle Chemical Mechanical Planarization of Wide Band Gap

Semiconductors” by A. Arjunan, D. Singh; SINMAT; Gainesville, FL.

--- POSTER PAPERS ---

5.J “SiCr Thin Film Resistor Integration Using Damascene TiN” by S. Drizlikh, S. Kolda and R.Tracy; NATIONAL SEMICONDUCTOR; South Portland, ME.

5.K “Polysilicon CMP for Non-CMOS Applications” by T. Pfau and R.L. Rhoades; ENTREPIX; Tempe, AZ.

Wednesday Lunch on Your Own

Not Provided by Conference

SESSION VI - 1:00 P.M. - 2:00 P.M.

VLSI MULTILEVEL INTERCONNECTION

DEDICATED TIME FOR CMP

POSTER PAPERS, EXHIBIT VIEWING

Invited Session

SESSION VII - 2:00 P.M. - 3:45 P.M.

VLSI MULTILEVEL INTERCONNECTION

C.M.P. DEFECTIVITY ISSUES

Chairman: Dr. Abhijit Chandra

IOWA STATE UNIVERSITY

Ames, Iowa

7.A “Oxide CMP as a Test Vehicle for Defectivity During CMP With Composite Polymer Core - Silica Shell Abrasives Designed for Scratch Reduction During Copper CMP” by S. Armini, C.M. Whelan and J.L. Hernandez; IMEC; Leuven, BELGIUM; and K. Maex; UNIV Of LEUVEN; Leuven, BELGIUM; and M. Moinpour; INTEL CORP; Santa Clara, CA.
Invited Paper

7.B “Nano-Scale Scratching in Chemical-Mechanical Polishing” by T. Eusner, N. Saka and J-H. Chun; MASSACHUSETTS INST. Of TECH; Cambridge, MA.
Invited Paper

7.C “Role of Multi-Scale Polishing Pad Response on Evolution of Scratches During CMP” by A. Bastawros and A. Chandra; IOWA STATE UNIV; Ames, IA.
Invited Paper

7.D “Stress and Slurry Chemistry Effects on Cracking and Damage Evolution During CMP Implications for Next Technology Nodes” by R.H. Dauskardt and T.S. Kim; STANFORD UNIV; Stanford, CA; Q. Zhong, M. Peterson and H. Tam; JSR MICRO; Sunnyvale, CA; and T. Konno; JSR MICRO; Yokkaichi, JAPAN.
Invited Paper

7.E “A Multi-Scale Predictive Model for Wafer Surface Evolution During a CMP Process Incorporating Slurry Evolution” by X. Wang, P. Karra, A. Chandra, A. Bastawros and R. Biswas; IOWA STATE UNIV; Ames, IA; and L. Yao; STRASBAUGH; San Luis Obispo, CA.
Invited Paper

--- POSTER PAPERS ---

7.F “Defectivity Study During Oxide CMP With Composite Polymer Core – Silica Shell Abrasive: The Effect of the Silica Particle Shape” by S. Armini and C.M. Whelan; IMEC; Leuven, BELGIUM; M. Moinpour; INTEL CORP; Santa Clara, CA; and K. Maex; KATHOLIEKE UNIV; Heverlee, BELGIUM.

SESSION VIII - 4:00 P.M. - 5:00 P.M.

VLSI MULTILEVEL INTERCONNECTION

C.M.P. PAD CONDITIONERS

Chairman: Dr. Robert Rhoades

ENTREPIX

Tempe, Arizona

8.A “Investigating the Effect of Diamond Properties on Pad Topography, Friction Force and Removal Rate in ILD CMP” by Y. Zhuang, L. Borucki and A. Philipossian; ARACA; Tucson, AZ; X. Wei, F. Sudargho, Y. Sampurno, G. Steward; UNIV Of ARIZONA; Tucson, AZ; and N. Rikita; MITSUBISHI; JAPAN.
Invited Paper

8.B “Development of Bending Fiber Conditioner in Chemical Mechanical Polishing” by T. Fujita; TOKYO SEIMITSU; Tokyo, JAPAN; D. Kamikawa; SHIBAURA INST. Of TECH.; Tokyo, JAPAN; T.K. Doi; SAITAMA UNIV; Tokyo, JAPAN.

8.C “PCD Planers for Dressing CMP Pads: The Enabling Technology for Manufacturing Future Moore’s Law Semiconductors” by J.C. Sung and Y.L. Pai; KINIK; Taiwan, R.O.C.; M.Y. Tsai and Y.S. Liao; NAT’L TAIWAN UNIV; Taiwan, R.O.C.

-- POSTER PAPERS --

8.D “The Organic Diamond Disk (ODD) for Chemical Mechanical Planarization” by J.C. Sung, C.S. Chou, Y.L. Pai, W. Huang and C.C. Wang; KINIK; Taiwan, R.O.C.

8.E “Low Cost Epoxy-Based Diamond Disk for Dressing CMP Pads” by J.C. Sung; KINIK; Taiwan, R.O.C.; M. Sung and B.G. Monteith; ADVANCED DIAMOND SOLN; San Francisco, CA.

8.F “The Wear Characteristics of Pad Conditioners for CMP Manufacture of Semiconductors” by H.Y. Chu; NAT’L TAIPEI UNIV Of TECH; Taiwan, R.O.C.; J.C. Sung, T.J. Hsiao, C. Lin and I.T. Liao; KINIK; Taiwan, R.O.C.

Thursday, March 8, 2007

SESSION IX - 9:00 A.M. - 10:00 A.M.

VLSI MULTILEVEL INTERCONNECTION

CMP CONDUCTORS, METROLOGY

& MODEL/SIMULATIONS

Chairman: Dr. Karey Holland

TECHCET LLC

Genoa, Nevada

CMP CONDUCTORS

9.A “Study of the Tungsten CMP Impact on Alignment and Overlay for 65 nm DRAM Technology” by K. W. Chung, C.Y. Huang, C.K. Lin; NANYA TECH; Taiwan, R.O.C.; U. Jahn, T. Ernst, U. Malkoc; QIMONDA; Dresden, GERMANY.

-- POSTER PAPERS --

9.B “Effects of WCMP Process on Surface Charging Mode of Electron Beam Inspection” by L.L. Lai, K. Xu, D. Deng and J. Ning; SEMI. MANUFACTURING INT.; Beijing, PRC.; H. Xiao, Y. Zhao, E. Ma and J. Jau; HERMES MICRO-VISION; Milpitas, CA.

CMP METROLOGY

9.C “Three-Dimensional CMP Metrology With Two-Way Symmetrical Scanning in Wide-Area Atomic Force Microscope” by K. Murayama, T. Morimoro and Y. Kunitomo; HITACHI; Ibaraki, JAPAN.

CMP MODEL & SIMULATIONS

9.D “A TCAD-Based Study of Fill Pattern and Via Fill Impact on Low-k Dielectric Stress” by A.B.Kahng and R.O. Topaloglu; UNIV Of CALIFORNIA; San Diego, CA.
Invited Paper

SESSION X - 10:15 A.M. - 12:15 P.M.

VLSI MULTILEVEL INTERCONNECTION

C.M.P. CONSUMABLES - SLURRY Part II

Chairman: Dr. Yuzhuo Li

CLARKSON UNIVERSITY

Potsdam, New York

10.A “New Slurries for ILD and STI CMP” by M. Kroell; DEGUSSA AG; Rodenbacher, GERMANY.
Invited Paper

10.B “Correlation Between Particle Force and Polishing Defectivity During Pump Induced Agglomeration of Slurries” by R. Singh; UNIV Of FLORIDA; Gainesville, FL.
Invited Paper

10.C “Development of Advanced Copper CMP Slurry for 45 nm Technology Node” by I.Yoshida, H. Kamiya, S. Takemiya, N. Nakazawa and A. Hayashi; ASAHI GLASS CO; Kanagawa, JAPAN.

10.D “Effects of Shear and Cavitation on Particle Agglomeration During Pumping of CMP Slurries Containing Silica, Alumina and Ceria Particles” by M.R. Litchy, D.C. Grant and R. Schoeb; CT ASSOC; Eden Prairie, MN.
Invited Paper

10.E “Next Generation Barrier CMP Slurry for 45 nm Node and Beyond” by C.L. Hsu, C.C. Huang; UNITED MICRO. CORP; Taiwan, R.O.C.; and Q. Ye, H. Li, R. Lavoie, C.F. Dai; ROHM & HAAS; Newark, DE.

10.F “New Chemistries for Low Stress Planarization of Ta/Ru Barrier Layers and Low-k Dielectrics” by A. Misra, D. Singh; SINMAT; Gainesville, FL.; and R.K. Singh; UNIV Of FLORIDA; Gainesville, FL.

--- POSTER PAPERS ---

10.G “Enhancement of CMP Slurry Filtration for Achieving Low CoO Solution” by C. Patel; ENTEGRIS; Billerica, MA.

10.H “High Resolution, High-Sensitivity Particle Size Analysis of Concentrated CMP Slurries Using the New Technique of Focused Light Extinction (FX)” by D. Nicoli, J. Wilmer, P. O’Hagan, K. Hasapidis, P. Toumbas; PARTICLE SIZING SYS; Santa Barbara, CA.

10.I “Low Defect Ceria-Based Slurries: Novel Selectivity, Slurry Characterization and Polishing Mechanisms” by B. Santora, H. Liu, B. Her, B. Kraft and C. Zedwick; FERRO ELECTRONICS; Penn Yan, N.Y.

10.J “On-Line Spectroscopic Monitoring of CMP Slurry Particles” by R. Carlone and R. Bryant; PARTICLE MEASURING SYS; Boulder, CO.

10.K “Fundamentals of Pump-Induced Slurry Agglom-eration During CMP of Copper/Low k Dielectrics” by R. Singh, F.C. Chang and S. Tanawade; UNIVERSITY Of FLORIDA; Gainesville, FL.

10.L “In-Situ UV Spectroscopic Hydrogen Peroxide Monitoring in CMP Slurry” by R. Bryant; PARTICAL MEAS. SYS.; Boulder, CO.

CMP-MIC LUNCHEON - 12:15 - 2:00 P.M.

“ CHEMICAL - MECHANICAL

POLISH: A HISTORICAL PERSPECTIVE”

Peter Singer

Editor-in-Chief

SEMICONDUCTOR INTERNATIONAL

Andover, MA

SESSION XI - 2:00 P.M. - 4:00 P.M.

VLSI MULTILEVEL INTERCONNECTION

C.M.P. PROCESS CONTROL

Chairman: Dr. Steve Holland

TECHCET LLC

Genoa, Nevada

11.A “Friction Force Monitoring for Advanced CMP Process Control” by Y. Yamada, M.Kawakubo, O. Hirai and N. Konishi; HITACHI; Tokyo, JAPAN.
Invited Paper

11.B “Face-Up Chemical-Mechanical Polishing: Theory and Experiments” by N. Saka and J.H. Chun; MASSACHUSETTS INST. Of TECH.; Cambridge, MA.
Invited Paper

11.C “In-Situ CMP Monitoring and Control Via Pad Surface Friction and Wear Data Collection” by J.H. Givens, M. Vinogradov; CENTER for TRIBOLOGY; Campbell, CA.

11.D “Kinematical Effects on Slurry Flow and Material Removal Rate in Face-Up CMP” C. Mau, N. Saka and J.H. Chun; MASSACHUSETTS INST. Of TECH.; Cambridge, MA.

11.E “Experimental Dynamics Characterization and Monitoring ofChemical Mechanical Planarization Process” by R. Komanduri, S. Bukkapatnam, P.K. Rao and U. Phatak; OKLAHOMA STATE UNIV; Stillwater, OK.
Invited Paper

11.F “In-Pattern Dummy Design and Copper ECD / CMP Process Co-Optimization” by H. Cai and D. Boning; MASSACHUSETTS INST. Of TECH; Cambridge, MA.

--- POSTER PAPERS ---

11.G “Advanced FEOL CMP and Integration Solution” by D.A. Hansen; UNITED SEMI; Sunnyvale, CA.

11.H “Quantitative Analysis on Wafer-Pad Contact Area in CMP” by H.Y. Kim, B.H. Kwon, J.K. Choi, M.K. Hong, B.U. Yoon, C. Hong, H. Cho and J.T.Moon; SAMSUNG ELECTRONICS; Yongin-City, KOREA.

11.I “The Role of Zonal Pressure Control in Chemical Mechanical Polishing” by P. Karra, A. Chandra, A. Bastawros; IOWA STATE UNIV; Ames, IA; and L. Yao, A. Strasbaugh; STRASBAUGH; San Luis Obispo, CA.

11.J “Investigations of Under / Over Polish Parameters That Influence Local and Global Topography at the 65 nm Technology Node” by S.Gaillard, O. Belmont, A. LeGouil and E. Sicurani; ST MICRO-ELECTRONICS; Crolles, FRANCE.