TWENTY
THIRD INTERNATIONAL
VLSI/ULSI MULTILEVEL INTERCONNECTION
CONFERENCE
September 26 - 28,
2006
ADVANCE PROGRAM
Tuesday, September 26, 2006
OPENING SESSION --- 8:30
A.M.
Welcoming Remarks by the General
Chairman
Dr. Thomas E. Wade
University of South
Florida
SESSION I ---
8:35 A.M.
KEYNOTE ADDRESSES
“ADVANCING
SILICON SCALING: 65 nm
TECHNOLOGY & CHALLENGES BEYOND”
Dr. Peng Bai
Vice
President
INTEL CORP.
Santa
Clara, California
“NEW DIMENSIONS
IN PERFORMANCE”
Kerry Bernstein
IBM WATSON
RESEARCH CTR.
Yorktown Heights, New York
Coffee Break 9:35 - 9:45 A.M.
“BEOL INTEGRATION FOR 45 & 32 nm
NODES: CHALLENGES & SOLUTIONS”
Dr. Roey Shaviv
NOVELLUS CORP.
San Jose, California
“3-D INTEGRATED CIRCUITS:
MYTHS AND MOTIVES”
Susan Vitkavage
SEMATECH
Austin, Texas
SESSION II - 10:45 A.M. -
12:15 P.M.
VLSI MULTILEVEL INTERCONNECTION
NOVEL/ DIELECTRIC SYSTEMS
Chairman: Alfred Grill
IBM WATSON RESEARCH CTR.
Yorktown Heights, New York
NOVEL SYSTEMS
2.A
“Air Gap Structures From Cu / Low-k
Damascene” by G. Smith,
L. Smith, S. Hosali and S. Arkalgud; SEMATECH, Austin, TX.
2.B
“CMOS Photonics Technology and
Applications” by C. Gunn;
LUXTERA; Carlsbad, CA.
(Invited Paper)
2.C
“Step-And-Flash Imprint Lithography
Enabling 32 nm Patterning for Unit Process Development”
by S.V. Sreenivasan, P. Schumaker, I. McMakin, D. Resnick, D. LeBrake
and J. Doering; MOLECULAR IMPRINTS; Austin, TX.
(Invited Paper)
--- POSTER PAPERS---
2.D
“Semiconductor on Diamond (SOD) for
System on Chip (SoC) Architectures”
by J.C. Sung, M.C. Kan and S.C. Hu; KINIK CO; Taiwan, R.O.C.; M. Sung,
B.G. Monteith; ADVANCED DIAMOND SOLN; San Francisco, CA.
DIELECTRIC SYSTEMS
2.E “Laser Spike Annealing: A
Novel Post-Porosity Treatment for Toughening of Low-k Organosilicates”
by W. Volksen, G. Dubois, A. Kellock, T.P. Magbitang, R.D. Miller; IBM
ALMADEN RES. CTR; San Jose, CA.; S. Cohen, E.E. Simonyi; IBM WATSON RES
CTR; Yorktown Heights, N.Y.; L. Ramirez; UNIV Of CALIFORNIA; Irvine, CA;
and Y. Wang; ULTRATECH; San Jose, CA.
(Invited Paper)
2.F
“Barrier-Free Interconnect Using Organic Low-k Dielectric” by N.
Maeda, Y. Takimoto and K. Funatsu; CASMAT; Tokyo, JAPAN; and K. Maejima,
M. Nakajima; SUMITOMO
BAKELITE; Tokyo, JAPAN
--- POSTER PAPERS---
2.G
“Effect of Annealing Temperature and
Contact Geometry on Stability of Contacts in Pre-Metal Dielectric Glass”
by F. Parhami; CYPRESS SEMI; San Jose, CA.
Box Lunches 12:15 - 1:30 P.M
SESSION III - 1:30 - 3:45
P.M.
VLSI MULTILEVEL
INTERCONNECTION
KEYNOTE PANEL - I
“ADVANCEMENTS IN 3-D
INTEGRATED CIRCUITS”
PANEL MODERATOR
Dr. John F.
McDonald
RENSSELAER POLYTECHNIC
INST.
PANEL MEMBERS
Cornelia K. Tsang
IBM WATSON RES CTR
Yorktown Heights, New
York
Jason Cong, Chmn.
UCLA Computer Science
Los Angeles, California
Wen-Chih Chiou
Exploratory Interconnect
Program
T.S.M.C.
Taiwan, R.O.C.
Craig L. Keast
MIT LINCOLN LABS
Cambridge, Massachusettes
Robert Patti
TEZZARON SEMI
Naperville,
Illinois
Bipin Rajendran
STANFORD UNIVERSITY
Stanford, California
A brief Questions & Answer period
will follow formal presentations
Coffee Break 3:45 - 4:00 P.M.
SESSION IV - 4:00 - 5:30 P.M
VLSI MULTILEVEL INTERCONNECTION
C.M.P. PROCESSES - PART I
Chairman: Dr. Stan
Tsai
APPLIED MATERIALS
Santa Clara, California
4.A
“CMP In-Situ Friction Force
Monitoring” by Y. Yamada,
M. Kawakubo and N.Konishi; HITACHI; Tokyo, JAPAN.
4.B
“CMP for 45 & 32 nm Nodes:
Challenges & Solutions”
by B. Bonner; NOVELLUS; San Jose, CA
(Invited Paper)
4.C
“Effects of Consumables on SiN
Erosion in STI CMP Process for Beyond 60 nm Node Technology”
by S.Y. Shih, C.M. Liao, J.Y. Ho, C.H. Kuo and C.R. Wu; NANYA TECH;
Taiwan, R.O.C.
4.D
“Metal Thickness Variations and Its
Impact on Design” by U.
Narasimha, P. Groves, A. Hill and Nagaraj NS; TEXAS INSTRUMENTS; Dallas,
TX.
4.E
“CMP for 3D-MIM Applications”
by C. Perrot, C. Cremer, Y. Loquet, B. Iteprat, M. Proust, C. Richard
and D. Benoit; ST MICROELECTRONICS; Crolles, FRANCE.
4.F
“Dishless and Erosion-Free Copper
Damascene Process” by B.T.
Lin; T.S.M.C.; Taiwan, R.O.C.
--- POSTER PAPERS---
4.G “Ceria Slurry Particle
Removal Optimization” by Y. Epshteyn, A.S. Lawing and J. Federowicz;
ROHM & HAAS; Phoenix, AZ.
4.H “Effective Dispersion of CMP
Slurry Abrasive Particles” by R.K. Singh; ENTEGRIS; Billerica, MA;
and B.R. Roberts; BOC EDWARDS; Santa Clara, CA.
4.I
“Characterization and Application of
Non-Porous Polyurethane Polishing Pad”
by H.W. Ha, S.Y. Kim, S.S. Jang, H.S. Kim, J.K. Lee, H.P. Kim, J.D.
Jeong, Y.S. Kim and J.H. Go; DONGBU ELECTRONICS; Gyeonggi, KOREA.
4.J
“How to Eliminate or Minimize the
Variation in Removal Rate Due to the Conditioner Age in Oxide CMP
Processes” by M. Hossain,
M. Goulding, T. Gandy, C. Taylor, A. Sidhwa and B.Y. Mao; ST
MICROELECTRONICS; Phoenix, AZ.
4.K
“Advanced Diamond Disk for
Electrolytic Chemical Mechanical Planarization”
by H. Ishizuka; KANAGAWA UNIV;
Taiwan, R.O.C.; E. Nishizawa; ISHIZUKA MAT’L; Taiwan, R.O.C.; J.C. Sung;
KINIK; Taiwan, R.O.C.; M. Sung; ADV DIAMOND SOLN; San Francisco, CA.
Wednesday, September 27, 2006
SESSION V - 8:00 - 9:15 P.M.
VLSI MULTILEVEL
INTERCONNECTION
KEYNOTE PANEL - II
“Copper/Low-k Advancements”
PANEL
MODERATOR
Yuzhuo Li
Clarkson Univ.
PANEL MEMBERS
Alfred
Grill, Mgr.
PECVD ULK Dielectric
Group
IBM WATSON RES
CTR
Yorktown Height, New York
Vincent Arnal
Adv. Cu/ULK Module
ST MICROELECTRONICS
Crolles 2 Alliance,
FRANCE
Gregory Smith
Interconnect Division
SEMATECH
Austin,
Texas
A brief Question & Answer period
will follow formal presentations
Coffee Break 9:15 - 9:30 A.M.
SESSION VI - 9:30 - 12:00 A.M.
VLSI MULTILEVEL
INTERCONNECTION
3-D
I.C. PROCESSES
Chairman: Dr. Cornelia K. Tsang
IBM WATSON RES. CTR.
Yorktown Heights, New York
6.A “Improved Manufacturability
of Cu Bond Pads and Implementation of Seal Design in 3D Integrated
Circuits and Packages” by K.N. Chen, C.K. Tsang, A.W. Topol, B.K.
Furman, D.L. Rath, A.M. Young, S. Purushothaman, W. Haensch; IBM WATSON
RES CTR; Yorktown Heights, N.Y.; and S.H. Lee, J.Q. Lu; RENSSELAER
POLYTECH INST.; Troy, N.Y.
(Invited Paper)
6.B “Point-to-Point 3-D
Interconnect Fabrication Using High Pressure Reflow of Aluminum Alloys”
by M. Khbeis and C. Bles, W.Metze; LAB for PHYSICAL SCIENCES; College
Park, MD; N. Goldman; UNIV Of MARYLAND; College Park, MD.
(Invited
Paper)
6.C “3-D Integration of
Integrated Circuits” by C. Keast, B. Aull, J. Burns, C. Chen, J.
Knecht, B. Tyrrell, K. Warner, B. Wheeler, B. Suntharlingam, D. Yost;
M.I.T. LINCOLN LABS; Cambridge, MA.
(Invited
Paper)
6.D “Tiled Diamond Cube
Substrates for 3D Vertical Integration of SoC Technologies” by J.C.
Sung, T.Y. Yen, M.C. Kan, S.C. Hu, M. Sung and B.G. Monteith; KINIK;
Taiwan, R.O.C.
6.E “A 3-Tier Asynchronous FPGA”
by D. Fang, C. LaFrieda, S. Peng and R. Manohar; CORNELL UNIV; Ithaca,
N.Y.
(Invited
Paper)
6.F“A 3D SOI SRAM Suitable for
Processor Integration” by J.F. McDonald, R.P. Kraft, P. Belemjian,
O. Erdogan, P. Jacobs and A. Zia; RENSSELAER POLYTECH. INST.; Troy, N.Y.
6.G “Breaking Rent’s Rule:
Opportunities for 3D Interconnect Networks” by W. R. Davis and C.
Mineo; NORTH CAROLINA STATE UNIV; Raleigh, N.C.
6.H “Stress-Induced Grain
Evolution for 3D - IC Interwafer Via Reliability” by M.O.
Bloomfield, D.N. Bentz, J.Q. Lu, R.J. Gutmann and T.S. Cale; RENSSELAER
POLYTECH. INST.; Troy, N.Y.
--- POSTER PAPERS---
6.I “A Slow Wave Photonic Crystal
Enhancement of Drude-Effect Light Modulators for Intra-Chip Optical
Interconnections Using 3D Wafer Bonding Techniques” by J.F.
McDonald, R.P. Kraft, J.R. Guo, P. Belemjian, O. Erdogan, P. Jacobs, A.
Zia; Y. Yim, M. Chu, J.W. Kim, J. Diao and J.Q. Lu; RENSSELAER POLYTECH.
INST.; Troy, N.Y.
[Wednesday Lunch on Your Own.
Not Provided by Conference]
SESSION VII - 1:00 - 2:15 P.M.
VLSI MULTILEVEL INTERCONNECTION
POSTER PAPER / EXHIBITION
DEDICATED VIEWING TIME
(Invited Session)
SESSION VIII - 2:15 - 5:00 P.M.
VLSI MULTILEVEL INTERCONNECTION
CONDUCTOR & RELIABILITY
SYSTEMS
Chairman: Michael Wedlake
SPANSION
Austin, Texas
CONDUCTOR SYSTEMS
8.A “Interconnect Challenges for
NOR Flash Memory Technology” by I. Hashim, N.M. Chang, E. Eliadis,
A. Friedman, V. Gorantla, Z. Guo, Y. Hsu, H. Lee, L.J. Ma, G.W. Ray, Y.
Shor and L. Zhao; INTEL CORP; Santa Clara, CA.
(Invited Paper)
8.B “Non-Contact Metal Cap
Thickness Metrology on Patterned Wafers” by L. Cunnane, A. Kiermasz;
METRYX; Bristol, UNITED KINGDOM; I. Ivanov, L. Hall, P. Little; BLUE29;
Sunnyvale, CA.
--- POSTER PAPERS ---
8.C “Characterization of Capping
Layers Effects on CoSi2 Formation” by J. Hsieh, I. Liao and J. Chen;
PROMOS TECH; Taiwan, R.O.C.
RELIABILITY ISSUES
8.D “Shortlength Effects on
Electromigration Lifetime of Copper Interconnect in 90 nm Low-k CVD ILD
Technology” by B.N. Agarwala, H.S. Rathore, J.J. Demarest, L.A.
Clevenger and C.C. Yang; IBM; Hopewell Jct., N.Y.
8.E “Stress Induced Metal Blister
and Void in Multilevel Interconnect” by D.K. Jeon, I.C. Baek, H.C.
Lee, J.W. Han and K.H. Kim; DONGBU ELECTRONICS; Chungbuk, KOREA.
8.F “Photo-Activated Galvanic
Corrosion of Copper Interconnects” by M. Wedlake; SPANSION; Austin,
TX.
(Invited Paper)
8.G “Studies of Post-Implant Ash
Induced Ring-Pattern Defects After Gate Poly and WSix Etch” by J.H.
Zhang and B. Stephenson; ST MICRO-ELECTRONICS; Carrollton, TX.
8.H “Oxidation Implications of
Copper Metallization in Low-k Dielectrics” by H.S. Rathore, B.N.
Agarwala, B. Engel, R. Procter, D. Nguyen, V. McGahay and L.A.
Clevenger; IBM; Hopewell Jct., N.Y.
(Invited Paper)
8.I “ILD Defect Reduction in
Copper BEOL Technologies” by K.S. Lam, A. Seshadri, C. Lee, A.
Evans, H. Kobeissi, B. Brennan, K. Harper, T. James, A. Gutierriz, S.
Hardin, F. Smith, E. Brannon; SPANSION; Austin, TX and J. Edgar,
NOVELLUS, San Jose, CA.
--- POSTER PAPERS ---
8.J “Impact on Via Instability
Due to Embedded Moisture” by K. Ritari, J. Darr, T. Gandy, A. Sidhwa
and B.Y. Mao; ST MICROELECTRONICS; Phoenix, AZ.
8.K “The PH3 Effect on GC Poly /
Wsix Process” by F. Chang, J.Chen, B.R. Ni, C.J. Liaw and W.P. Nien;
PROMOS TECH; Taiwan, R.O.C.
8.L “Development of an Advanced
Process Control System for Base Pressure Detection for Endura Metal
Deposition Tool” by J. DeGraffenreid, N. Slaney, T. Gandy and A.
Sidhwa; ST MICROELECTRONICS; Phoenix, AZ.
8.M “Study of the Chamber Process
Kit Impact on Temperature Characterization for Hot Metal Deposition
Process” by M. Willbrand, Ardy Sidhwa, S. Melosky and B.Y. Mao; ST
MICROELECTRONICS; Phoenix, AZ; and N. Narendrnath, S. Chimni, B. Sinha,
B. Laibinis and M. Tajik; APPLIED MATERIALS; Santa Clara, CA.
8.N “Multiple Failure Analysis
Applications Using Strasbaugh nOvation” by E. Beaton and L. Yao;
STRASBAUGH; San Luis Obispo, CA.
8.O “Bonding Issues Related to
Probe Needle Mark Size on Aluminum Bond Pads” by G. Kuhel, T. Rudman
and A. Sidhwa; ST MICROELECTRONICS; Phoenix,AZ
8.P “Novel Method of
Quantification Using AFM to Understand Hillock Density in Bottom Plate
of Metal-Insulatior-Metal Capacitors” by Q.M. Lu, M. Kalaga, S.
Guisinger, X. Breurec and K. Dennis; ST MICRO; Phoenix, AZ.
Thursday, September 28, 2006
SESSION IX - 8:30 - 9:45 P.M.
VLSI MULTILEVEL INTERCONNECTION
KEYNOTE PANEL - III
“Pattern & Lithography
Advancements”
PANEL
MODERATOR
Dr. Yakov Shor
INTEL CORP.
Kiruat Gat, Israel
PANEL MEMBERS
Dr. Nicholas K. Eib
LSI LOGIC (former)
Milpitas, California
“Potential Solutions for 193 nm
Lithography Challenges at 45 and 32 nm”
Dr. Robert N. Castellano
INFORMATION NETWORK
New Tripoli, Pennsylvania
“Forecasting Lithography for 32 & 22
nm Nodes”
Dr. Reza Sadjadi
LAM RESEARCH CORP.
San Jose, California
“Post Lithography Feature Size
Reduction -
A Novel Approach to Patterning
Sub-Resolution Features”
A brief Question & Answer period
will follow formal presentations
Coffee Break 9:45 - 10:00
A.M.
Invited Session
SESSION X - 10:00 A.M. - 12:00 P.M.
VLSI MULTILEVEL INTERCONNECTION
D.F.M. / D.F.Y.
ISSUES
Chairman:
Dr. Valeriy Sukharev
PONTE SOLUTIONS
Mountain View, California
10.A “Circuit Level Assessments
of the Reliability of Copper / Low-k Interconnect Technologies” by
C.V. Thompson; MASSACHUSETTS INST. Of TECH; Cambridge, MA.
(Invited
Paper)
10.B “Computing Critical Area for
VLSI Layouts: Analysis Techniques and Tools” by I. Koren; UNIV. Of
MASSACHUSETTS; Amherst, MA.; H. Adamyan; PONTE SOLN; Mountain View, CA.
(Invited
Paper)
10.C “DFM for Fabless
Manufactures on Advanced Process Nodes” by R. Radojcic and M. Nowak;
QUALCOMM; San Diego, CA.
(Invited
Paper)
10.D “Pattern Density Effect in
Via/Contact Etch - Full Chip Analysis” by V. Sukharev and N.
Khachatryan; PONTE SOLN; Mountain View, CA.
(Invited
Paper)
10.E “Mask Optimization to
Increase Process Margins of Optical Lithography” by Y. Granik;
MENTOR GRAPHICS; San Jose, CA.
(Invited
Paper)
2006 VMIC AWARDS LUNCHEON
Thursday, September 28; 12:00 -
1:30 P.M.
“Competing Technologies for the 32
nm Generation and Beyond”
Peter Singer
Editor-In-Chief
SEMICONDUCTOR INTERNATIONAL
Reed Business Information
Andover,
Massachussetts
SESSION XI - 1:15 - 5:00 P.M.
VLSI MULTILEVEL INTERCONNECTION
C.M.P. PROCESSES - Part II
Chairman: Dr. Sharath Hosali
SEMATECH
Austin, Texas
11.A “Scaling of CMP Performance
of Periodic Nanometer Sized Surface Structure” by H. Tzeng and J.
Li; HITACHI GST; San Jose, CA.
11.B “The Impact of a Novel
Slurry Conditioner on Copper and STI CMP Performance” Y. Li and C.
Burkhard; CLARKSON UNIV; Potsdam, N.Y.; M. Serafin, N. Nelson and R.
Olmsted; Oakdale, MN.
11.C “Study of CMP Process
Performance for Copper / SiLK Interconnects Using New Barrier Slurries”
by S. Balakumar; INST. Of MICROELECTRONICS; SINGAPORE; C.S. Lim;
NANGYANG TECH UNIV; SINGAPORE; G. Koh; ROHM & HAAS; SINGAPORE.
11.D “Effect of Slurry
Temperature on Surface Defects and Tribology During CMP” by V.R.
Kakireddy, R. Mudhivarthi and A. Kumar; UNIV. Of SOUTH FLA; Tampa, FL.
11.E “The Role of Post-CMP
Cleaning Solution Additives in Minimizing Silica Slurry Adhesion on
Copper, Tantalum and TEOS-Deposited SiO2 Surfaces” by M. E. Stawasz,
M. Darsillo, S.K. DiMascio, J. Barnes; ATMI; Dansbury, CT.
11.F “Self-Aligned CMP
Integrated Study of 70 nm Node NAND Flash Memory on Floating Gate
Electrode” by C.Y. Ho, C.H. Lien; NAT’L TSING HUA UNIV; Taiwan,
R.O.C.; D.Z. Wang, C.N. Wu, K.C. Huang, K.K. Hsiao; POWERCHIP SEMI;
Taiwan, R.O.C.
11.G “Tribo-Chemical Modeling of
Copper CMP” by S. Tripathi, F. Doyle and D. Dornfeld; UNIV Of
CALIFORNIA; Berkeley, CA.
11.H “CMP Pad Design for
Ultra-Low-k Compatible Copper CMP Process” by R. Carpio, J. Pham and
F. Tolic; ATDF; Austin, TX; and S. Hymes, R. Bajaj; SEMIQUEST; San Jose,
CA.
11.I “Correlation Between Pad
Structure and CMP Performance” by Y. Li, K. Cheemalapati and C.
Burkhard; CLARKSON UNIV; Potsdam, N.Y.; W. Jun, I. Kodaka, H. Atsushi,
K. Toshihiro and K. Hozumi; MIPOX INT’L; Hayward, CA.
11.J “Effects of Pad Features
on Motor Current EPD Signal and the Performance of STI CMP Process”
by C.H. Kuo, C.Y. Ho, C.Y. Tsai, S.Y. Shih, C.R. Wu, J.P. Lin and P.I.
Lee; NANYA TECH; Taiwan, R.O.C.
--- POSTER PAPERS ---
11.K “Advanced Polycrystalline
Diamond Pad Conditioners For Future CMP Applications” by J.C. Sung,
C. S. Chou; KINIK; Taiwan, R.O.C.; M. Sung, B.G. Monteith; ADV. DIAMOND
SOLN; San Francisco, CA; H. Ishizuka; KANAGAWA UNIV; Yokohama, JAPAN.
11.L “Impact of Environmental
Temperature on the Performance of Copper CMP Slurries” by K.
Cheemalapati, D. Bundi, V. Duvvuru and Y. Li; CLARKSON UNIV; Potsdam,
N.Y.; L. Yao and A. Dalrymple; STRASBAUGH; San Luis Obispa, CA.
11.M “InnoPad - A New Pad
Technology” by O. Hsu, M. Jin, D. Wells, J. Aldeborgh; INNOVENT
TECH; Peabody, MA.
11.N “TW1311 Implement in 300
mm Production Line for Tungsten CMP at PROMOS” by C.Y. Lin, J.C.
Tung, H.T. Chen; PROMOS TECH; Taiwan, R.O.C.; L. Nguyen, J. Mendonca and
T. West; THOMAS WEST; Sunnyvale, CA.
11.O “Searching for BTA
Alternatives for Metal CMP” by S. Govindaswamy and Y. Li; CLARKSON
UNIV.; Z. Wu, Y. Li, X. Chen; SUN YAT-SEN UNIV.; Guangzhoum, CHINA.
11.P “Performance Based Post CMP
Uniformity Inspection” by M. Babazadeh, J. Vickers, J. Estabil, G.
Johnson, G. Steinbrueck, N. Pakdaman, M.B. Shemirani; TAU-METRIX;
Sunnyvale, CA; W. Doedel, O. Henry, E. Braud; CNET-ST; Crolles, FRANCE;
C. Spanos; UNIV Of CALIFORNIA; Berkeley, CA.
SESSION XII
VLSI MULTILEVEL INTERCONNECTION
MEM’s & MODEL/SIMULATION
PROCESSES
MEM’S PROCESSING
--- POSTER PAPERS ---
12.A “Design Analysis and
Fabrication of a MEMS Lateral Microactuator” by C.C. Chin, Z.M. Xiao
and J.M. Miao; NANYANG TECH; Rep of SINGAPORE.
MODEL/SIMULATION
PROCESSES
12.B “A Sum-Over-Paths
Impulse-Response Moment-Extraction Algorithm for IC Interconnect
Networks: Verification, Uncoupled RLCM Lines” by Y.L. LeCoz, D.
Krishna; RENSSELAER POLYTECH INST.; Troy, N.Y.; and D.M. Petranovic;
MENTOR GRAPHICS; Wilsonville, OR.
12.C “Mathematical Modeling to
Simulate the Defects Caused by CMP on Ebara F-REX 300 and AMAT Reflexion”
by H.T. Chen, C.Y. Lin, J.C. Tung; PROMOS TECH; Taiwan, R.O.C.; L.
Nguyen, J. Mendonca; THOMAS WEST; Sunnyvale, CA.
NOTICE TO AUTHORS OF
POSTER PAPERS
Plan to put ALL posters for ALL SESSIONS up on
Tuesday, September 26, before 9:30 am at the location designated (Check
at Conference Registration Desk). Poster boards will be provided as
indicated in author kits. Be available AT YOUR POSTER to answer
questions during Session VII (from 1:00 - 2:15 pm on Wednesday). Plan
to remove your poster on Thursday afternoon from 2 - 3 pm, September 28.