ELEVENTH INTERNATIONAL
C.M.P. PLANARIZATION
FOR ULSI MULTILEVEL INTERCONNECTION
February 21 - 23, 2006
Tuesday, February 21, 2006
OPENING SESSION - 8:30 A.M.
Welcoming Remarks by General Chairman
Dr. Thomas E. Wade
University of South Florida
SESSION I -- 8:40 A.M.
KEYNOTE ADDRESS
“WILL CMP CONTINUE TO ENABLE
FUTURE TECHNOLOGIES?”
INTEL CORPORATION
Hillsboro, Oregon
(Coffee Break 9:15 - 9:30 AM)
SESSION II -- 9:30 A.M.
KEY PANEL - I
“WHAT ARE THE KEY ISSUES
FOR CMP AT 45 nm?”
PANEL MEMBERS
Victor Souw, INTEL
Janos Farkas, FREESCALE
Duane Boning, M.I.T.
Mike Smayling, APPLIED MATERIALS
Brian Brown, NOVELLUS
A brief Question & Answer period will follow formal presentations.
SESSION III - 11:15 A.M. - 12:15 P.M.
ELECTRO CMP PROCESSES
Chairman: Dr. Duane Boning
M.I.T.
Cambridge, MA
3.A “eCMP of Copper Overburden”by S. Aksu, I. Emesh and B. Basol; ASM NUTOOL; Fremont, CA.
3.B “Effect of Electrolytes During Electrochemical Polishing Process on Tribological, Structural and Surface Chemical Characteristics of Copper”by S. Mudhivarthi, A. Kumar; UNIV Of S. FLORIDA; Tampa, FL; P. Zantye; INTEL; Hillsboro, OR.; H. McCrabb & E.J. Taylor, FARADAY TECH.; Clayton, OH.
3.C “Copper Behavior in Electro-Chemical Mechanical Planarization” by M. Kulkarni & H. Liang; TEXAS A & M; College Station, TX.
Box Lunches - 12:15 - 1:00 P.M.
Visit Industrial Exhibition/Poster Presentations
SESSION IV - 1:00 - 3:30 P.M.
CMP PROCESS CHARACTERIZATION
Chairman: Dr. Janos Farkas
Crolles, France
4.A “CMP Experience in High Volume Manufacturing of 90 nm Node Flash Technology” by M. Delavega, Y. Shor, B. Yardeni, A. Peleg, M. Mitlin, U. Gavish, Z. Sternberg, E. Aboody; INTEL CORP.; Kiryat Gat, ISRAEL.
Invited Paper
4.B “Overview of CMP Process Control Strategies” by L. Karuppiah, A. Ravid, B. Swedek, W.Y. Hsu; APPLIED MATERIALS, Santa Clara, CA.
Invited Paper
4.C “In Situ Measurements of the Coefficient of Friction and Drag Force During Chemical Mechanical Planarization” by C. Rogers, V. Manno, J. Vlahakis, C. Gray; TUFTS UNIV.; Medford, MA.; C. Barns, INTEL; Portland, OR.; M. Moinpour, INTEL; Santa Clara, CA.; S. Anjur; CABOT MICRO; Aurora, IL.; A. Philipossian, UNIV Of ARIZONA; Tucson, AZ.
4.D “Advanced CMP for Enabling Silicon Carrier Integration with Through-Vias and Find Pitch Wiring” by C. Tsang, D. Canaperi, J. Tornello, P. Buchwalter & D. Rath; IBM WATSON RES. CTR.; Yorktown Heights, N.Y.
Invited Paper
4.E “Extendibility of CMP Process to Cu / p-Low-k Interconnect Fabrication” by T. Nishioka, H. Yano, G. Minamihaba, D. Fukushima, S. Seta; TOSHIBA; Yokohama, JAPAN.
Invited Paper
4.F “Interfacial Fluid Pressure Measurements at a Rotating Head and Platen Interface During CMP” by S. Danyluk, A. Osorno, I. Yoon & S. Tsiareshka; GEORGIA INST. Of TECH.; Atlanta, GA.
4.G “Alignment of Plating Profile and Removal Profile - The Handshake Between CMP and ECP” by U. Stockgen, S. Wehner, A. Preube, M. Keil; AMD; Dresden, GERMANY; and M. Nopper, F. Mauers-berger; G. Marxsen; AMD; Saxony, GERMANY.
Invited Paper
4.H “Guidelines for Improving CMP Manufacturing Metrology Equipment Software”by M. Wedlake, C. Lansford; SPANSION; Austin, TX.
--- POSTER PAPERS ---
4.I “Impact of Multi-Zoned Head of Optimization of 300 mm Post Polish Profile” by J. Sorooshian, A.B. Hopcus; N.J. Kalainoff; P.C. Pedigo & D.G. Hooper; INTEL CORP; Rio Rancho, N.M.
4.J “Advantages of Non-Contact Optical Metrology for Characterization of CMP Processes” by L. Bond, K. Freischlad, S. Tang, M. Plemmons; ADE; Tucson, AZ; P. Burke, C. Falk, R. Broyles; LSI LOGIC; Gresham, OR.
4.K “Heat Transfer Model to Estimate Temperature Distribution on a Wafer Surface During a Steady State CMP Process” by S.R. Mudhivarthi; J.C. Lallave, M.M. Rahman, A. Kumar; UNIV Of S. FLORIDA; Tampa, FL.
4.L “Investigation of Motor Current EPD System Monitoring A Direct STI CMP Process With Ceria-Based Slurry for Various STI Gap-Fill Schemes” by C.H. Kuo, S.Y. Shih, C.R. Wu, J.P. Lin and P.I. Lee; NANYA; Taiwan, R.O.C.
SESSION V - 3:45 - 5:45 P.M.
VLSI MULTILEVEL INTERCONNECTION
C.M.P. DIELECTRIC
Chairman: Kashmir S. Sahota
AMD
5.A “Direct-Polish STI CMP Process for Next Generation Gap Fill Technologies” A. Iyer, G. Leung, G. Menk, P. McReynolds, B. Zhang, A. Rosenbusch, G. Prabhu, R. Jackson, N. Ingle, T. Winson, Z. Yuan, V. Banthia; APPLIED MATERIALS, Sunnyvale, CA.
5.B “Characterization, Modeling and Process Optimization of Low Pressure ILD CMP” by J. Zabasajja, T. Merchant; FREESCALE; Chandler, AZ
Invited Paper
5.C “Pitch-Dependence in Oxide CMP” by R. Rzehak; INFINEON TECH; Dresden, GERMANY.
Invited Paper
5.D “A Fixed Abrasive STI Process for 200 mm Rotary Polishing” by C.K. Huang, E. Gleason; MICRO-CHIP TECH; Gresham, OR.; J. Gagliardi; 3M; St. Paul, MN.
Invited Paper
5.E “Dual Nitride Polish Stop for Chemical Mechanical Planarization of Shallow Trench Isolation” by J. Woloszyn, D. Hahn, V. Gallacher, S. Park; FAIRCHILD SEMI; South Portland, ME.
5.F “Chip Scale Prediction of Nitride Erosion in High Selectivity STI CMP” by J. Choi, S. Tripati, D. Dornfeld; UNIV Of CALIFORNIA; Berkeley, CA.; D. Hansen, CYPRESS SEMI; Santa Clara, CA.
Invited Paper
--- POSTER PAPERS ---
5.G “Evaluation of a Post Tungsten Polish Oxide Buff” by P.J. Beckage & J. Groschopf; SPANSION; Austin, TX.
5.H “Ceria Slurry for Direct STI Application: Past, Present and Future Generations” by C. Yu, S. Lane, B. Mueller, S. Lawing, P. Flanagan, K. Lindemann; ROHM & HAAS; Newark, DE.
5.I “Study of the Loading Effect of Cerium Oxide Based Slurry in STI CMP Process and Its Improvement” by J.W. Lee, B.U. Yoon, J.K. Choi, J.S. Park, H.Y. Kim, C.K. Hong, H.K. Cho & J.T. Moon; SAMSUNG; Gyeonggi, KOREA.
5.J “Developing Oxide Chemical Mechanical Polish Process at Passivation Step” by J.H. Zhang, T. Ninh, F. Ferrari, B. Stephenson & G. Magsamen; ST MICROELECTRONICS; Carrollton, TX.
5.K “Improvement of With-in-Die and With-in-Wafer Planarity Using STI CMP Slurry with ‘Step-Stopping and Ultra High Selectivity’ Mechanism” by C.W. Nam, J. Shen; CABOT MICRO; Aurora, IL.
5.L “Empirical Model of SiN Erosion in the Direct STI CMP Process for Advanced Nanometer Generation” by C.H. Kuo, S.Y. Shih, C.M. Liao, C.R. Wu, J.P. Lin, P.I. Lee; NANYA; Taiwan, R.O.C.
5.M “Integration Challenges for Advanced Direct STI CMP Application: Consumables, Processes and Endpoint Detection Techniques” by C. Yu, S. Lane, B. Mueller, S. Lawing, K. Lindemann, P. Flanagan & M.J. Kulp; ROHM & HAAS; Newark, DE.
-- LATE NEWS PAPER --
5.N “STI CMP Process Uniformity Control With In-Line AFM Depth Metrology” by T. Bao; VEECO; Santa Barbara, CA; and R. Romani, M. Ercole; TEXAS INSTRUMENTS; Dallas, TX.
SESSION VI -- 8:00 A.M.
“EMERGING TECHNOLOGIES
FOR CMP”
Paul Fischer, INTEL
Uwe Stoeckgen, AMD
Naga Chandrasekaran, MICRON
Paul Feeney, CABOT MICRO
Cathie Markham, ROHM HAAS
Hsin-Hsien Lu, TSMC
A brief Question & Answer Period will follow formal presentations.
(Coffee Break - 9:30 A.M. - 9:45 A.M.)
SESSION VII - 9:45 A.M. - 12:25 P.M.
VLSI MULTILEVEL INTERCONNECTION
CMP MODEL & SIMULATION - Part I
Chairman: Dr. Uwe Stockgen
AMD
7.A “Modeling of Friction Evolution During STI CMP as Endpoint Signals” by X. Xie, D. Boning; M.I.T.; Cambridge, MA; K. Devriendt; IMEC; Leuven, BELGIUM; A.S. Lawing; ROHM & HAAS; Phoenix, AZ.
7.B “Copper CMP Characterization and Modeling” by A. Guyot, S. Kordic, M. Mellier; PHILIPS SEMI; O. Belmont, C. Ajoux; ST MICROELECTRONICS; M. Zaleski; FREESCALE; and Y. Danto, A. Touboul; IXL LABS; Crolles, FRANCE.
Invited Paper
7.C “New Tribochemical Studies at the Nanometer Scale: Synergisms of Mechanical and Chemical Forces” by T. Dickinson; WASHINGTON STATE U.; Pullman, WA.
Invited Paper
7.D “Multi Scale Physical CMP Simulation Frame-work for ECAD” by T. Yoshida; YNT; Yamaguchi, JAPAN.
Invited Paper
7.E “Analysis and Modeling of Nanotopography Impact in Blanket and Patterned Wafer Polishing” by X. Xie, D. Boning; M.I.T.; Cambridge, MA; F. Meyer, R. Rzehak; INFINEON; Dresden, GER-MANY; P. Wagner; WACKER SILTRONIC; Mnchen, GERMANY.
Invited Paper
7.F “A Model of Dishing & Erosion” E. Paul, D. Richardson, A. Lerario; STOCKTON COLLEGE; Pomona, N.J.
Invited Paper
7.G “Microscopy-Based Description of CMP Pad Microtexture and Asperity-Scale Modeling of Slurry Flow Dynamics” by G.P. Muldowney, R. Palaparthi; ROHM & HAAS; Phoenix, AZ; D.P. Tselepidakis; S.G. Natu; V. Vikas; FLUENT; Phoenix, AZ.
Invited Paper
7.H “Causal Analysis of Conditioner Design Factors on Removal Rates in Copper CMP” by L. Borucki, Y. Zhuang; ARACA; Tucson, AZ.; N. Rikita, T. Yamashita, R. Kikuma; MITSUBISHI; Tokyo, JAPAN; A. Philipossian; UNIV Of ARIZONA; Tucson, AZ.
--- POSTER PAPERS ---
7.I “Modeling and Simulation of Non-Uniform Nanometer Interconnect Structures Based on Scattering-Parameter” by J.S. Wang; ALPHA MICRO; Taiwan, R.O.C.
7.J “Closed Loop Control Modeling Algorithms for Fully Automated CMP” by C.F. Wang, C.M. Liu, L.K. Chou; WINBOND; Taiwan, R.O.C.
7.K “Silicon Characterization of Dummy-Metal-Filled Nanometer Interconnect Structures for High-Frequency Scattering Parameter Circuit Simulations” by J.S. Wang; ALPHA MICRO; Taiwan, R.O.C.; K.J. Chang; TSING HUA UNIV; Taiwan, R.O.C.; J.J. Yao; NAT’L TAIWAN UNIV; Taiwan, R.O.C.
Wednesday Lunch on Your Own
Not Provided by Conference
SESSION VIII - 1:15 P.M. - 2:30 P.M.
VLSI MULTILEVEL INTERCONNECTION
DEDICATED TIME FOR CMP
POSTER PAPERS, EXHIBIT VIEWING
SESSION IX - 2:30 P.M. - 5:45 P.M.
VLSI MULTILEVEL INTERCONNECTION
C.M.P. POST CLEAN &
NOVEL PROCESSES
Chairman: Dr. Cliff Spiro
Cabot Microelectronics
Aurora, Illinois
9.A “Study of Time-Dependent Degradation of Anti-Oxidants in Post-Cu CMP Cleaning Chemistry” by S. Paul, H.M. Wang, K. Musaka; EBARA TECH; Albany, N.Y.; S.X. Qiao, C. Watts & R. Stevens; ATMI; Allentown, PA.
9.B “Post Copper CMP Cleaning of Low-k Surfaces Using Resin Particles” by N. Kurashima, G. Minamihaba, S. Yamamoto, T. Nishioka & H. Yano; TOSHIBA; Yokohama, JAPAN.
9.C “Evaluation of Various Cleaning Methods to Reduce the Post Oxide CMP Defect Density” by S.M. Gallus, M. Maue, T. Schest, T. Zollitsch; INFINEON TECH; Regensburg, GERMANY.
9.D “Watermark Improvement in Post CMP Cleaning on Copper / Low-k Structures” by M. Fujii, R. Furui & S. Shibuki; SONY; Kanagawa, JAPAN.
--- POSTER PAPERS ---
9.E “Comparison of Various Methods for Evaluating the Efficiency of BTA Removal in Copper PCMP Cleaning Development” by J. Barnes, E. Walker, M. Hughes, J. Liu; ATMI; Allentown, PA.
NOVEL CMP APPLICATIONS
9.F “CMP Processing Issues for MEMS Fabrication Technology” by A.L. Moy & D. Hetherington; SANDIA NAT’L LABS; Albuquerque, NM.
Invited Paper
9.G “Snapshot of CMP Technology Evolution for Non-Traditional Applications” by R. Rhoades; ENTREPIX; Tempe, AZ.
Invited Paper
9.H “Pyrogenic Metal Oxide for Use in Future CMP Applications” by M. Kroell; DEGUSSA; Hanau, GERMANY.
Invited Paper
9.I “CMP Application for a 3-D Semiconductor Device” by S.N. Peng, B.T. Lin, S.C. Wang & W.L. Fang; T.S.M.C.; Taiwan, R.O.C.
9.J “CMP Compatible for Both Copper/Low-k Level in a 90 nm Technology and Thick Copper Level in an RF Technology” by Y. Loquet, C. Perrot, B. Iteprat, J.C. Giraudin, P. Bouillon; ST MICRO; Crolles, FRANCE.
9.K “Control of the Multi-Scale Non-Uniformities in Copper CMP by Face-Up Polishing” by K. Noh, N. Saka & J.H. Chun; M.I.T.; Cambridge, MA.
--- POSTER PAPERS ---
9.L “Trajectory Analysis for a Dual Side Polisher Used in the CMP Process” by T. Kasai; CABOT MICRO; Aurora, IL.
SESSION X
VLSI MULTILEVEL INTERCONNECTION
C.M.P. CONSUMABLES - PART I
-- POSTER PAPERS --
10.A “Advanced Pad Conditioners for Copper CMP” by K. Teo, K. Lim, K.C. Loh & L. Zazzera; 3M ELECTRONICS; SINGAPORE; and S. Balakumar; INST. Of MICRO; SINGAPORE.
10.B “Evaluation of Novel Chemical Additive as an Inhibiting Agent in Copper CMP” by S. Govindaswamy, Y. Li; CLARKSON UNIV; Potsdam, N.Y.
10.C “The Adequate Diamond CMP Pad Conditioner for Copper / Low-k Material” by T. Ooi, M. Sagawa, Y. Nishioka; ASAHI DIAMOND; Tokyo, JAPAN.
10.D “High-Resolution, High-Sensitivity Particle Size Analysis of Concentrated CMP Slurries Using the New Techniques of Focused Light Extinction and Scattering” by D.F. Nicoli, P. Toumbas, Y.J. Chang, J.S. Wu, K. Hasapidis; PARTICLE SIZING SYS; Santa Barbara, CA.
10.E “Experimental and Theoretical Investigation of Slurry Chemical & Mechanical Characteristics in Copper Polishing” by Y. Zhuang, L. Borucki; ARACA; Tucson, AZ; M. Keswani, R. Zhuang, A. Philipossian; UNIV Of ARIZONA; Tucson, AZ; M. Lacy, C. Spiro; CABOT MICRO; Aurora, IL.
10.F “Particle Size Distribution Determination of CMP Abrasive Particles Using Density Gradient Stabilized Centrifugal Sedimentation” by M. Kamiti; CABOT MICRO; Aurora, IL.
10.G “Methods for Determination of CMP Pad Life: Simulation by Conditioning Versus Actual Wafer Passes” by L. Charns; JSR MICRO; San Jose, CA.
10.H “Studies of Advanced Pad Conditioners” by J.C.M. Sung; KINIK; Taiwan, R.O.C.; N. Gitis, S. Kuiry, M. Vinogradov & V. Khosla; CTR. For TRIBOLOGY; Campbell, CA.; E. Nishizawa, T. Toganoh; TOMEI DIAMOND; Tochigi, JAPAN.
10.I “Effect of Temperature on Pad Conditioning Process During CMP” by S. Mudhivarthi; A. Kumar; UNIV Of S. FLORIDA; Tampa, FL; N. Gitis, S. Kuiry, M. Vinogradov; CTR. For TRIBOLOGY; Campbell, CA.
10.J “The Effect of Additive Concentration on Zeta Potential in Ceria and Silica-Based Slurries” by B. Santora, B. Kraft, D. Merricks and B. Her; FERRO; Penn Yan, N.Y.
10.K “The In-Situ Dressing of CMP Pad Conditioners With Novel Coating Protection” by J.C. Sung, K. Kan; KINIK; Taiwan, R.O.C.
10.L “Pumping Technologies for CMP Slurries” by R.K. Singh; ENTEGRIS; Billerica, MA.
SESSION XI -- 8:00 A.M.
KEY PANEL - III
“CURRENT AND FUTURE NEEDS
FOR CMP METROLOGY”
PANEL MEMBERS
Linda Bond, ADE
Robert Newcomb, FILMETRICS
Li Wu, TIMBRE (TEL)
John Santucci, NOVA
Michael Wedlake, SPANSION
A brief Question & Answer period will follow formal presentations.
(Coffee Break - 9:30 A.M. - 9:45 A.M.)
SESSION XII - 9:45 A.M. - 12:25 P.M.
VLSI MULTILEVEL INTERCONNECTION
CMP MODEL & SIMULATION
& CMP CONDUCTOR PROCESSES
Chairman: Dr. Abhijit Chandra
IOWA STATE UNIVERSITY
Ames, Iowa
CMP MODEL & SIMULATION - II
(Invited Session - Organized by Session Chair)
12.A “Experimental Investigation Into Material Removal Characteristics of CMP” by R. Komanduri, S. Bukkapatnam; OKLAHOMA STATE U.; Stillwater, OK.
12.B “Synergy Between Chemical Dissolution and Mechanical Abrasion During CMP of Copper” by W. Che; ST.GOBAIN; Boston, MA; A. Bastawros, A. Chandra; IOWA STATE U.; Ames, IA.
12.C “An Investigation of Transient CMP Wafer Surface Heating at the Pad Groove Scale” by G.P. Muldowney; ROHM & HAAS; Newark, DE.
12.D “Granular Flow Simulation of CMP” by D. Arbelaez & T. Zohdi; UNIV Of CALIFORNIA; Berkeley, CA.
12.E “Scratch Generation Probability in CMP” by C. X. Wang, P.J. Sherman, A. Chandra; IOWA STATE UNIV.; Ames, IA.
12.F “Modeling Wafer Surface Damage Caused During CMP” by T.A. Ring; UNIV Of UTAH; Salt Lake City, UT; P. Feeney, J. Kasthuriran, S. Li, D. Boldridge, J. Dirksen; CABOT MICRO; Aurora, IL.
CMP CONDUCTOR PROCESSES
12.G “Metal CMP Defect Reduction Strategies” by M. Buehler & A. Miller; INTEL; Hillsboro, OR.
Invited Paper
12.H “Controlling Removal Rate and Trace Metal Contamination in Polysilicon Films During CMP" by J. Dysard, J. Dirksen, P. Feeney; CABOT MICRO; Aurora, IL; C. Barns, J. Bennett, P. Fischer; INTEL; Hillsboro, OR; and M. Moinpour, INTEL; Santa Clara, CA.
Invited Paper
-- POSTER PAPERS --
12.I “Influence of Solid H2O2 and pH on Tantalum Polishing Kinetics” by S. Li & J. Fletcher; CABOT MICRO; Aurora, IL.
SESSION XIII - CMP-MIC LUNCHEON
12:25 - 2:00 P.M.
“ IN SEARCH OF BETTER BUSINESS
MODELS FOR ELECTRONIC MATERIALS ”
Michael A. Fury
Vice President for Research & Development
DUPONT EKC TECHNOLOGY
Hayward, California
SESSION XIV - 2:00 P.M. - 4:00 P.M.
VLSI MULTILEVEL INTERCONNECTION
C.M.P. CONSUMABLES & RELIABILITY
Filmetrics
San Diego, California
14.A “Effects of Slurry Characteristic on Post Cu CMP Stacking Behavior” by H.H. Lu, J.Y. Song, H.H. Kuo, T.Y. Hwang, Y.H. Chen, S.M. Jeng, C.H. Yu and M.S. Liang; T.S.M.C.; Taiwan, R.O.C.
Invited Paper
14.B “Frictional, Thermal and Kinetic Characterization of a Novel Ceria Based Abrasive Slurry for Silicon Dioxide CMP” by Y. Zhuang, L. Borucki, A. Philipossian; ARACA; Tucson, AZ; M. Keswani, D. Rosales-Yeomans, H. Lee; UNIV Of ARIZONA, Tucson, AZ; M. Ennahali, G. Michel, B. Laborie; KEMESYS; Tucson, AZ.
14.C “Pad Topography Effects on CMP With Emphasis on Copper / Low-k” by A. De Feo, S. Lee & D. Dornfeld; UNIV. Of CALIFORNIA, Berkeley, CA.
14.D “Investigation of Some Key Factors That Influence Step Height Reduction Efficiency and Defectivity During Metal CMP” by Y. Li; CLARKSON U.; Potsdam, NY.
Invited Paper
14.E “Characterization of Physical and Chemical Changes in Polyurethane Pad Surface During CMP: Thermo Set (PU) vs. Thermoplastic (TPU) by A. Prasad, E.E. Remsen; CABOT MICRO; Aurora, IL.
14.F “Novel Low-Abrasive Slurries and Abrasive-Free Solutions for Copper CMP: Enhancement of Polishing Performance Through Controlled Modification of Interfacial Properties” by I. Belov, J.Y. Kim, M. Perry, P. Watkins, T. Moser & K. Pierce; PRAXAIR; Indianapolis, IN.
-- POSTER PAPERS --
14.G “Planarization Efficiency With Different Abrasive Particles and Chemical Additives During Copper Process” by D.H. Eom, J.H. Rhee, M.G. Song, Y.G. Lee, H.S. Hyun & S.I. Lee; SAMSUNG; Suwon, KOREA.
14.H “Novel Non-Abrasive Slurries for Copper CMP” by D. Ng, H. Liang; TEXAS A & M; College Station, TX; and K. Cheemalapati, Y. Li; CLARKSON UNIV; Potsdam, NY.
14.I “Standardized Tests of Pad Conditioners” by N. Gitis, S. Kuiry, M. Vinogradov & V. Khosla; CTR. for TRIBOLOGY; Campbell, CA.
14.J “Asperity Size Distribution Near Wafer Features During CMP” by C. Gray, C. Rogers, V. Manno, J. Vlahakis; TUFTS UNIV.; Medford, MA; C. Barns, M. Moinpour; INTEL; Santa Clara, CA.; A. Anjur; CABOT MICRO; Aurora, IL.; L. Borucki; ARACA; A. Philipossian; U Of ARIZONA; Tucson, AZ.
14.K “Ceria-Based Slurries Exhibiting Reverse-Prestonian Behavior” by D. Merricks, B. Santora, B. Her & S. Frink; FERRO; Penn Yan, N.Y.
14.L “Evaluation of an Ultra-Flat Ceramic Based CMP Conditioning Disk” by M. Bubnick, T. Namola, S. McGregor, K. Torrance, R. Wielonski; ABRASIVE TECH; Lewis Center, OH.
14.M “Effect of Additives in CMP Slurries on the Selectivity of Low-k Dielectric Layers in Barrier CMP” by S. Takemiya, N. Nakazawa; ASAHI GLASS; Kanagawa, JAPAN; S. Shinmaru; SEIMI CHEMICAL; Kanagawa, JAPAN.
14.N “The Next Generation Diamond Pad Conditioner for CMP” by J.C. Sung; KINIK; Taiwan, R.O.C.
CMP RELIABILITY ISSUES
14.O “The Trenching Phenomenon During the Barrier Polish Step in a Copper Damascene Technology” by T. Bormann; DRESDEN UNIV Of TECH; Dresden, GERMANY; and G. Springer; INFINEON; Dresden, GERMANY.
14.P “A Study of the Mechanism and Yield Impact of the Light Induced Tungsten Ring Defect” by C. Yim, B. Brennan, K. Cox, T. James, M. Meyer, N. Yazdani; P. Beckage; SPANSION; Austin, TX.
14.Q “Edge-Over-Erosion in Tungsten CMP” by R. Vacassy & Z. Chen; CABOT MICRO; Aurora, IL.
-- POSTER PAPERS --
14.R “A Study on Darkened Tungsten Local Interconnect Lines and Contacts” by P.J. Beckage, J. Herrera, J. Darilek, T. Werner; SPANSION; Austin, TX.
14.S “A Simple and Effective Method to Monitor Oxide CMP Micro Scratches” by M. Yu, S.H. Shih, K.I. Huang, H.B. Lu, C.C. Yang; UNITED MICRO CORP; Taiwan, R.O.C.
14.T “Investigation of Edge-Over-Erosion in Copper CMP” by K. Cheemalapati, V. Duvvuru, D. Bundi & Y. Li; CLARKSON UNIV; Potsdam, N.Y.; and S. Han, H. Li; SKW ASSOC; Santa Clara, CA.
14.U “Effect of Polish Byproducts on Copper CMP Process” by Y. Jung, J. Han, G. Leem, T. Kim and I.S. Cho; SAMSUNG; Kyungii, KOREA.
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