“Interconnect Process Extendibility From 90 to 45 nm Node”
Dr. Nobuyoshi Kobayashi; Selete Backend Program Mgr.
Keynote Address - 1 (Tuesday AM)

“Moore’s Law Plus - What Will Be Needed
In Interconnect, Other Than Scaling,
From An Applications Perspective”
Dr. Takayasu Sakurai; University Of Tokyo
Keynote Address 2 (Tuesday AM)

“Interconnect: Challenges to the 2D Paradigm”
Dr. Sitaram Arkalgud; Sematech Director of Interconnect
Keynote Address - 3 (Tuesday AM)

“Silicon IC Technology and Manufacturing Innovations
for the Past and the Next 30 Years”
Dr. Hiroshi Iwai; Tokyo Institute of Technology
Keynote Address - 4 (Tuesday AM)

“Practical Integration of Low-k Dielectrics to 45 nm for
Product Development”
Dr. Takeshi Nogami; Sony / IBM Microelectronics
VMIC Awards Luncheon (Thursday @ Noon)