2.A
“New Spin-On Oxycarbosilane Low-k Dielectric Materials With
Exceptional Mechanical Properties” by G.
Dubois, T. Magbitang, W. Volksen and R.D. Miller; IBM ALMADEN; San
Jose, CA.
2.B
“Porous Ultra Low-k Process Technology Develop-ment for 65 / 45 nm
Nodes”by C.H. Yao, C.C. Jeng, W.K. Wan, K.C. Lin, M.S. Liang, H.H.
Lin, C.H. Huang, K.S. Chi, T.C. Huang, C.S. Huang, Y.C. Wang, M.D.
Lei, C.C. Hsia; TSMC; Taiwan, R.O.C.
(Invited
Paper)
2.C
“Design of a New Low-k Dielectric Which Meets the Goals of the
2002
ITRS Road Map”by
J. Economy and Y. Huang; UNIV. Of ILLINOIS; Urbana, IL.
2.D
“Novel Polysilsesquioxane Systems for Ultralow-k Dielectric Films With
High Modulus, Low CTE and Closed-Pore Morphology” by D.Y. Yoon,
E.S. Park, J.H. Park, J.H. Shim, J.K. Lee; SEOUL NAT’L UNIV.; Seoul,
KOREA; H.W. Ro, H.J. Lee, C. Soles; N.I.S.T.; Washington, DC; H.W.
Rhee; SOGANG UNIV; Seoul, KOREA; D.W. Gidley; UNIV. Of MICHIGAN; Ann
Arbor, MI.
---
POSTER PAPERS---
2.E
“Preparation and Characterization of the Ultralow Dielectric Constant
Porous Silica Films” by C.H. Yang, W.L. Yang, L.M. Lin and K.S.
Chia; FENG CHIA UNIV; Taiwan, R.O.C.
2.F
“Low-k Materials for DRAM BEOL” by A. Thies, U. Kahler, J.C. Cigal;
INFINEON TECH; Dresden, GERMANY.
Box
Lunches 12:05 - 1:15 P.M.
(Invited Session)
SESSION
III - 1:15 - 2:55 P.M.
VLSI MULTILEVEL
INTERCONNECTION
THREE
DIMENSIONAL SYSTEMS - Part I
Chairman:
Dr. John F. McDonald
RENSSELAER POLYTECHNIC
INST.
Troy,
New York
3.A
“Process and Results: 3D - IC Integration” by S. Gupta, M.
Hilbert, S. Hong and R. Patti; TEZZARON SEMI; Naperville, IL
3.B
“On-Wafer Optical Interconnectivity Using 3D Integration of Optical
and Electronic Integrated Circuits” by P.D. Persans, J.Q. Lu, R.J.
Gutmann and A. Gennett; RENSSELAER POLYTECH; Troy, N.Y.; S. Ponoth;
IBM MICRO; East Fishkill, N.Y.; R. Garrelts; UNIV. Of NEBRASKA;
Kearny, NE.
3.C
“CMOS Transistor Processing Compatible With Monolithic 3-D
Integration” by B. Rajendran, D.J. Witte, R.F.W. Pease; STANFORD
UNIV.; Stanford, CA.; R.S. Shenoy; IBM ALMADEN; San Jose, CA.; N.S.
Chokshi, R.L. DeLeon, G.S. Tompa; AMBP TECH; Tonawanda, N.Y.
(Invited
Paper)
3.D
“Circuit and System Dimensions of 3-D Integration” by C.C. Liu, I.
Ganusov, M. Burtscher, and S. Tiwari; CORNELL UNIV.; Ithaca, N.Y.;and
L. Xue; SPANSION, Sunnyvale, CA.
(Invited
Paper)
3.E
“Modeling Thermal Stresses in 3D IC Interwafer Vias” by D.N. Bentz,
J. Zhang, M. Bloomfield, J.Q. Lu, R.J. Gutmann and T.S. Cale;
RENSSELAER POLYTECH; Troy, N.Y.
(Invited
Paper)
---
POSTER PAPERS---
3.F
“R3CAD - Tools
For 3-D Integrated Circuit Design” by L. McIlrath; R3 LOGIC;
Cambridge, MA.
3.G
“Adhesion Wafer Bonding of GaN, InP and Si With Passivated GaAs
Substrates by Selective SeS2 Treatment
and its Dielectric Properties” by P. Premchander and Y.T. Lee;
GWANGJU INST; Gwangju, SOUTH KOREA.
Coffee Break 2:55 - 3:10
P.M.
SESSION
IV - 3:10 - 5:50 P.M.
VLSI MULTILEVEL
INTERCONNECTION
CONDUCTORS & CMP PROCESS
Chairman:
Dr. Ara Philipossian
UNIVERSITY OF ARIZONA
Tucson,
Arizona
--
CONDUCTOR SYSTEMS --
4.A
“Size Effects and the Future of Interconnect Scaling” by G.
Schindler, M. Engelhardt and M. Traving; INFINEON TECH; Dresden,
GERMANY.
(Invited
Paper)
4.B
“A Study of Copper Gap Filling Challenges and Potential Solutions for
65 nm and Beyond” by K.H. Lin, C.L. Hsu, Y.C. Chen, S.J. Chen, Y.D.
Tsai, C.S. Chen, C.C. Huang, S.F. Tzou; UNITED MICRO. CORP.; Taiwan,
R.O.C.
(Invited
Paper)
4.C
“Bottom-Up Filling Using Organic Additives in Copper Electroless
Deposition” by C.H. Lee, S.K. Cho and J.J. Kim; SEOUL UNIV; Seoul,
KOREA.
4.D
“Electroplating of Low Resistivity Copper Inter-connection Layer for
65 nm Node” by T. Hara; HOSEI UNIV.; Tokyo, JAPAN.
(Invited
Paper)
---
POSTER PAPERS ---
4.E
“An Impact of Chamber Pressure on the Residual Etch Rate During the
Tungsten Etch Back Process Step” by J.H. Zhang; ST MICRO;
Carrollton, TX.; L.O. Sim, S.A.B.Lei, M. Nag, Y. Dao; ST MICRO;
SINGAPORE; A. Sidhwa; ST MICRO; Phoenix, AZ.
4.F
“Advanced Barrierless Metallization: Good Thermal Stability Copper
Films” by J.P. Chu; NAT’L TAIWAN OCEAN UNIV; Taiwan, R.O.C.; and
C.H. Lin; CHIN-MIN INST. Of TECH; Taiwan, R.O.C.
4.G
“A Study of an Intermittent Mechanical Particle Generation in the
Tungsten Etch Back Chamber” by J.H. Zhang, J. Helland, C.
Lawrence. S.L. Toh, B. Stephenson, G. Magsamen and A. Sidhwa; ST
MICROELECTRONICS; Carrollton, TX.
4.H
“M1 WL Baseline Improvement” by B.R. Ni, E. Zuo, S. Hone, J. Chen
and W.P. Chiu; PROMOS TECH; Taiwan, R.O.C.
4.I
“Elimination of Condensate Defects After the Tungsten Etch Back
Process” by J.H. Zhang, B.P. Zhao, B. Stephenson, G. Magsamen and
A. Sidhwa; ST MICROELECTRONICS; Carrollton, TX.
-- CMP
PROCESSES --
4.J
“Impact
of Multi-Level Chemical Mechanical Polishing on 90 nm and Below"
by D. White, A. Gower; PRAESAGUS; Campbell, CA.
(Invited
Paper)
4.K
“CMP Process Control for 65 nm and Beyond” by L. Karuppiah, A.
Manens, B. Swedek and L. Chen; APPLIED MATERIALS; Santa Clara, CA.
(Invited
Paper)
4.L
“Using a Multi-Scale Analysis to Predict Chemical Mechanical
Polishing” by F. Higgs III, E. Terrell; CARNEGIE MELLON UNIV;
Pittsburg, PA.
(Invited
Paper)
4.M
“Physics and Modeling of Fundamental CMP Phenomena” by L. Borucki;
ARACA; Tucson, AZ; A.
Philipossian, Y. Zhuang; UNIV Of ARIZONA; Tucson, AZ.
(Invited
Paper)
Wednesday, October 5, 2005
SESSION
V - 8:00 - 10:00 A.M.
VLSI MULTILEVEL
INTERCONNECTION
DIELECRIC CMP & COMPLETE PROCESSES
Chairman: Dr. David A. Hansen
CYPRESS SEMICONDUCTOR
San Jose, California
--
DIELECTRIC CMP --
5.A
“Prediction and Characterization of Direct STI CMP on Selected
Features Using HDP Oxide” by D.A. Hansen, I. Gilboa, B.
Banachowicz, S. Levy and L. Lee; CYPRESS SEMI; San Jose, CA.
(Invited
Paper)
5.B
“Low-k Film Removal Control Via CMP Slurry and Processing” by C.L.
Hsu, W.C. Su, C.C. Huang; UNITED MICRO CORP; Taiwan, R.O.C.; Q. Ye, T.
Thomas, H. Li, R. Lavoie, C.F. Dai; ROHM & HAAS; Newark, DE.
5.C
“Implications of Wafer Size Scale-Up on Frictional, Thermal and
Kinetic Attributes of ILD CMP Process” by D.R. Yeomans, L. Lujan
and A. Philipossian; UNIV Of ARIZONA; Tucson, AZ; L. Borucki; ARACA;
Tucson, AZ; T. Doi; SAITAMA UNIV; Sakura, JAPAN.
--- POSTER PAPERS ---
5.D
“A Novel Method to Estimate Direct STI CMP Capability” by J. Nair
and H. Geller; TOWER SEMI; Migdal Haemek, ISRAEL.
5.E
“The Effects of Wafer Topography After STI Fill on Ceria Slurry STI
CMP for Beyond 110nm Gener-ation” by S.Y. Shih, J.J. Cheng, C.H.
Kuo, C.R. Wu and J.P. Lin; NANYA TECH; Taiwan.
5.F
“Driving Optimum Planarization Performance in Direct STI CMP Process”
by C. Yu, S. Lane, B. Mueller, S. Lawing, P. Flanagan, K. Lindeman;
ROHM & HAAS; Newark, DE.
5.G
“‘Stoichemistry’ Response of Polishing Profile on a Four-Zone Control
Head” by C.M. Liao, S.Y.Shih, C.R. Wu and J.P. Lin; NANYA TECH;
Taiwan, R.O.C.
--
COMPLETE PROCESS --
5.H
“BEOL Evaluation for 32 nm Technology Node and Beyond” by R. Yu,
J. Doyle, S. Purushothaman, R. Wisnieff, C.K. Hu, M.B. Rothwell, J.
Bucchignano, G. Gibson, A. Neira, K. Kwietniak, M. Lofaro; IBM;
Yorktown Heighs, NY.
(Invited
Paper)
5.I
“Challenges for Copper/Ultra Low-k Interconnect Using All
Spin-On-Dielectric Materials” by S.Y. Arase, N. Maeda, H.
Kawakami, N. Ichiki, K. Sumiya, Y. Homma, ; CASMAT; Tokyo, JAPAN; H.
Saito, M. Tada; SUMITOMO BAKELITE; Yokohama, JAPAN; K. Shirato, T.
Kokubo; JSR CORP; Ibaraki, JAPAN.
(Invited
Paper)
5.J
“Process Integration Using Self-Aligned Electroless Technology”by
I.C. Ivanov, A. Kolics and R. Rolkens; BLUE29; Sunnyvale, CA.
(Invited
Paper)
---
POSTER PAPERS ---
5.K
“Interconnect Technology for Next Generation of SoC” by W. Li and
B. Mbouombouo; LSI LOGIC; Milpitas, CA.
-- LATE
NEWS PAPER --
5.L
“Practical Buffer Insertion for
Deep
Submicron Process Post Route Optimization”
by J.S.
Wang; Smart IC; Taiwan, R.O.C.; and K.J. Chang; NAT’L TSING HUA UNIV;
Taiwan, R.O.C.
Coffee Break 10:00 - 10:15
A.M.
SESSION
VI - 10:15 A.M. - 12:15 P.M.
VLSI MULTILEVEL
INTERCONNECTION
RELIABILITY ISSUES
Chairman: Dr. Hazara Rathore
IBM MICROELECTRONICS
Hopewell
Junction, New York
6.A
“Use of Wafer Level Voltage Ramp in Detecting Potential Time Dependent
Dielectric Breakdown Problems in 90 nm Cu / CVD Low-k Interconnects”
by K. Chanda, H. Rathore, C.C. Yang, L. Clevenger, V. McGahay, T.
Spooner, C. Barile; IBM; Hopewell Jct., NY; J. Gill; IBM; Essex
Junction, VT.
(Invited
Paper)
6.B
“Stress-Induced Voiding in Copper / Low-k Inter-connects” by J.M.
Paik, Y.C. Joo; SEOUL NAT’L UNIV; Seoul, KOREA.
(Invited
Paper)
6.C
“Electromigration Induced Buildup and Thinning in Passivated Metal
Lines: Observations and Modeling” by P.A. Flinn, STANFORD UNIV;
Stanford, CA.; and J.C. Doan, REFLECTIVITY; Sunnyvale, CA.
(Invited
Paper)
6.D
“Mechanical Behavior of Copper / Low-k Stacks With Different Barrier
Layers” by V.N. Sekhar, S. Balakumar; INST. Of MICROELECTRONICS;
SINGAPORE; S.K. Sinha, A.A.O. Tay; NAT’L UNIV Of SINGAPORE.
6.E
“Stress Migration Reliability of Copper Interconnect Stacked Via
Structures With Adjacent Copper Plates in Low-k Dielectrics” by
D.B. Nguyen, K. Chanda, H. Rathore, J.J. Demarest, D. Edelstein,
L.Clevenger, C.C. Yang; IBM MICRO; Hopewell Jct., NY.
(Invited
Paper)
6.F
“Characterization and Modelling of Stress-Induced Voiding in Copper
Interconnect for 90 nm and 65 nm Technologies” by M. Gregoire, P.
Vannier, E. Sabouret; ST MICRO; Crolles, FRANCE; S. Kordic, S.M.
d'Heres, X. Federspiel, S. Orain; PHILIPS; Crolles, FRANCE; and M.
Ignat; INPG-LTPCM; Crolles, FRANCE.
(Invited
Paper)
---
POSTER PAPERS ---
6.G
“TDDB Reliability Improvement of Copper - Comb Capacitors With Bilayer-Structured
SiC Dielectric Barriers” by C.H. Yang, W.L. Yang, K.S. Hsia and
L.M. Lin; FENG CHIA UNIV.; Taiwan, R.O.C.
6.H
“Timing Derived Current for Signal Net Reliability Assessment” by
J. Daio, J.R. Guo, J. McDonald; RENSSELAER POLYTECH; Troy, NY; J.
Venuto, T. Bucelot; IBM WATSON; Ossining, NY; L. Zhu; ANHUI ELECTRIC;
Anhui, Peoples Republic of CHINA.
6.I
“Effect of Chip Guard Ring Design and Properties of Inter-Layer
Dielectric Film on Chip-to-Package Reliability” by F. Parhami;
CYPRESS SEMI; San Jose, CA.; and
S. Pan; OPTIMAL CORP; San Jose, CA.
6.J
“The Mechanism Study of Standby Current Failure in Semi Tool” by
T.S. Cheng, J. Su; MACRONIX; Taiwan.
6.K
“Thermo-Mechanical Reliability of High End Flip Chip BGA Package:
Comparison Heat Spreader and Motherboard Construction” by S.H.
Kim, H. Park, K. Suzuki; NEC ELECTRONICS; Santa Clara, CA.
[Wednesday Lunch on Your Own Not
Provided by Conference]
SESSION
VII - 1:00 - 2:15 P.M.
VLSI MULTILEVEL
INTERCONNECTION
POSTER
PAPER / EXHIBITION
DEDICATED VIEWING TIME
(Invited Session)
SESSION
VIII - 2:15 - 3:55 P.M.
VLSI MULTILEVEL
INTERCONNECTION
DIELECTRIC SYSTEMS - Part II
Chairman: Dr. Robert D. Miller
IBM ALMADEN RESEARCH CTR.
San Jose, California
8.A
“Porous Low-k Dielectric Films Extraction and Restoration With
Supercritical CO2 Technology
for 65nm and Beyond Applications” by W.J. Wu, C.Y. Wang, J.C. Hu,
W.C. Chiou, J. Wang, C.H. Yu and M.S. Liang; T.S.M.C.; Taiwan, R.O.C.
8.B
“Mechanical and Dielectric Characterization of Low-k Porous
Organosilicates” by W. Volksen, T.P. Magbitang, G. Dubois, Y. Lee,
P.J. Brock and R.D. Miller; IBM ALMADEN; San Jose, CA.; E.E. Simonyi;
IBM WATSON; Yorktown Heights, NY; and L. Ramirez; UNIV Of CALIFORNIA;
Irvine, CA.
8.C
“Hybrid Porous and Dense Dielectric Stacks - BEOL Process Integration
for 65 and 45 nm Nodes” by D. Frye, J. Dominowski, J. Waeterloos,
M. Mills; DOW CHEMICAL; Midland, MI; L. Archer; SEZ AMER.; Phoenix,
AZ; R. Stevens; ATMI; San Jose, CA.
(Invited Paper)
8.D
“Lower-k Dense SiCOH Integration for 65 nm Node” by S. Lane,T.
Nogami; IBM MICRO; Hopewell Jct., NY.
(Invited
Paper)
8.E
“Multilevel Interconnection and Isolation for Electro-static MEMS
Using Embedded Benzocyclobutene in Silicon Process” by A. Modafe,
N. Ghalichechian, R. Ghodssi; UNIV. Of MARYLAND; College Park, MD.
(Invited
Paper)
--- POSTER PAPERS ---
8.F
“Investigation of BPSG Gap-Fill Ability on High Aspect Ratio
Structures” by C.Y. Wang, P.Y. Chang, C.T. Yang, C. Kuo, A. Ku;
PROMOS TECH; Taiwan, R.O.C.
8.G
“Low Temperature Silicon Dioxide Deposition and Characterization”by
H. Chatham, K. Williams, T. Lazerand, J. Owyang and H. Treichel; AVIZA
TECH; Scotts Valley, CA.
8.H
“Characterization of Cell Capacitor by Employing Re-Oxide/Nitride NO
Dielectric for Advance Trench DRAM” by C.K. Kao, C.M. Chang, C.M.
Kuo, C.Y. Wang and A. Ku; PROMOS TECH; Taiwan, R.O.C.
Coffee
Break 3:55 - 4:10 P.M.
SESSION
IX - 4:10 - 5:45 A.M.
VLSI MULTILEVEL
INTERCONNECTION
CMP
PROCESSES
Chairman: Dr. Ara
Philipossian
UNIVERSITY OF ARIZONA
Tucson,
Arizona
CMP
RELIABILITY ISSUES
9.A
“On the Mechanisms of Chatter Scratch Generation in CMP” by N.
Chandrasekaran; MICRON TECH; Boise, ID; and R. Komanduri; OKLAHOMA
STATE UNIV; Stillwater, OK.
(Invited
Paper)
9.B
“Influence of CMP Slurries and Post-CMP Cleaning Solutions on Defects
in SiOC Films and TDDB Reliability” by N. Konishi; HITACHI; Tokyo,
JAPAN.
(Invited
Paper)
9.C
“Closed-Loop, Design-Driven Optimization of Multilevel Interconnect
and CMP Fill” by P. Gupta, A.B. Kahng; UNIV Of CALIFORNIA; San
Diego, CA; O.S. Nakagawa, P. Sharma; BLAZE DFM; San Diego, CA.
(Invited
Paper)
---
POSTER PAPERS ---
9.D
“Effect of Slurry Flow Rate and Polishing Pressure on Dishing and
Non-Uniformity During Copper CMP” by S.R. Mudhivarthi, A. Kumar;
UNIV Of SOUTH FLORIDA; Tampa, FL; S. Kuiry, N. Gitis; CTR for
TRIBOLOGY; Campbell, CA.
9.E
“Impact of Transportation Time Between Platens During CMP on Product
Reliability” by Y.Y. Soh, I.C. Lim, D.K. Shukla, T.L. Neo and I.S.
Goh; SYS. on SILICON MFG; SINGAPORE.
9.F
“Characterization of Backgrind Damage Layer Depth and Stress
Relief CMP” by R.L. Rhoades; ENTREPIX; Tempe, AZ; and S. Krall;
SEMIGRIND; Chandler, AZ.
9.G
“IMD Via Rc Improvement by Oxide Buff Parameter Tuning” by H.C.
Sun, S.Y. Yang, W.Y. Lin, C.W. Dai, W.C. Liaw, G.Y. Jiang, K.W. Lee,
Y.F. Wang; Y.L. Chang; VANGUARD INT’L; Taiwan, R.O.C.
9.H
“CMP Process Uniformity and Retaining Ring Lapping Characterization”
by N.T. Leong, C. K. Wei, S.Y. Yee and W. Bing; SYS. on SILICON
MFG; SINGAPORE.
9.I
“Improvement of Cu / M1 Single Damascene Performance by Optimizing ILD
/ W-Plug CMP Integration” by C.Y. Ho, C.C. Hung; I.T.R.I.; Taiwan,
R.O.C. and C.H. Lien; NAT’L TSING HUA UNIV; Taiwan, R.O.C.
-- CMP
CONSUMABLES --
9.J
“Next Generation Copper CMP Slurries for Ultra Low Defect, Topography
and Cost of Ownership” by P. Lefevre, C. Poutasse, S. Rader, K.
Ina, K. Hori; FUJIMI CORP; Tualatin, OR.
(Invited
Paper)
9.K
“Tunable Low-Shear Copper CMP Pads: Purpose-Built Pad Engineering
Solutions” by P.K. Roy, M. Deopura, S. Misra and E. Hwang; NEOPAD
TECH; Sunnyvale, CA.
(Invited
Paper)
---
POSTER PAPERS ---
9.L
“Comparison of Polymer and Stainless Steel Sintered Abrasive Diamond
Pad Conditioners” by K. Teo, K. Lim, K.C. Loh; 3M; SINGAPORE; and
T. Engfer, D. Pysher, C. Loesch and L. Zazzera; 3M; St. Paul, MN.
9.M
“Handling and Filtration Characterization of SiLECT 6000 STI CMP
Slurry” by R.K. Singh and C.R. Wargo; MYKROLIS; Billerica, MA; B.R.
Roberts; BOC EDWARDS; Santa Clara, CA; and R. Viscomi, M. Federau;
CABOT MICRO; Aurora, IL.
9.N
“Self-Stopping Ceria Based Slurries for STI and ILD Polishing:
Novel Formulation and Mechanistic Understanding”by B. Santora, D.
Merricks, H. Goodman, S. Frink and B. Her; FERRO ELECTRONICS; Penn Yan,
NY.
9.O
“The Effect of Retaining Ring Fasteners on Wafer Uniformity in
Orbital CMP Polishers” by A. Yohannan, P. Carlier, C. Taylor, A.
Sidhwa, S. Taduri, M. Goulding and T. Gandy; ST MICRO-ELECTONICS;
Phoenix, AZ.
9.P
“A New Low Defectivity Planarizing Pad for Barrier CMP” by T.
Buley, P. Gopalan, D. Ventura and H. Rayle; ROHM & HAAS; Newark, DE.
-- LATE
NEWS PAPER --
9.Q
“High-Resolution, High-Sensitivity Particle Size Analysis of
Concentrated CMP Slurries Using the New Techniques of Focused Light
Extinction and Scattering” by D.F. Nicoli, P. Toumbas, Y.J. Chang,
J.S. Wu, K. Hasapidis; PARTICLE SIZING SYS; Santa Barbara, CA.
-- CMP
PROCESS ISSUES --
9.R
“Measurement of Diamond Conditioner Microwear” by L. Borucki, Y.
Zhuang; ARACA; Tucson, AZ; Y. Sampurno, A. Philipossian; UNIV. Of
ARIZONA; Tucson, AZ; and T. Merchant, J. Zabasajja; FREESCALE SEMI;
Austin, TX.
---
POSTER PAPERS ---
9.S
“An Investigation into Effect of Pad Conditioning in CMP for
Semiconductor Manufacturing” by K. Cox, C. Nauert, F. Smith. T.
Tang, C. Brannon, S. Endle, C. Yim, H. Gu, V. Wenner, M. Wedlake, M.
Addington, D. Lorek, W. Spooner, D. Lantz and C. Raeder; SPANSION;
Austin, TX.
9.T
“Effect of Slurry Injection Position on Slurry Mixing, Friction,
Removal Rate and Process Temperature During Copper CMP” by Y.
Sampurno, A. Philipossian; UNIV Of ARIZONA; Tucson, AZ; and L. Borucki;
ARACA; Tucson, AZ.
Thursday, October 6, 2005
(Invited Session)
SESSION
X - 8:00 - 9:40 A.M.
VLSI MULTILEVEL
INTERCONNECTION
THREE
DIMENSIONAL SYSTEMS - Part II
Chairman: Dr. John F. McDonald
RENSSELAER POLYTECHNIC
INST.
Troy,
New York
10.A
“Evaluation of 3D Processor Memory Chip-Stacks” by J.F. McDonald,
R.P. Kraft, P.M. Belemjian, O. Erdogan, P. Jacobs, A. Zia; R.J.
Gutmann, A.Y. Zheng, K. Rose and J.Q. Lu; RENSSELAR POLYTECH; Troy,
NY.
(Invited
Paper)
10.B
“Parylene X: A Candidate Cross-Linkable Chemical Vapor Depositable
Polymer for Wafer-to-Wafer Bonding” by J.J. Senkevich, B.P. Carrow,
B.W. Woods, R.E. Murray; BREWER SCIENCE; Rolla, MO.
10.C
“Wire-Delay Reduction Analysis of a 3-Tier, 8-Point
Fast-Fourier Transform 3D-IC” by W.R. Davis, H. Hua, A. Sule, C.M.
Steer; NORTH CAROLINA STATE UNIV; Raleigh, NC.
10.D
“Zias: Vertical Wires in 3-D Memory Devices” by V.Dunton; MATRIX
SEMI; Santa Clara, CA.
10.E
“Wafer-Level 3D Integration Technology Platforms for ICs and MEMS”
by F. Niklaus; ROYAL INST OF TECH; Stockholm, SWEDEN; and J.J.
McMahon, J. Yu, S.H. Lee, J.Q. Lu, T.S. Cale and R.J. Gutmann;
RENSSELAER POLYTECH; Troy, NY
10.F "Assembly Technology for Three-Dimensional (3D) Integrated
Circuits (ICs)" by A.W. Topol, D.C. La Tulipe, L. Shi, S.M. Alam,
D.J. Frank, S.E. Steen, J. Vichiconti, D. Posillico, M. Cobb, S. Medd,
S. Goma, D. DiMilia, R. Joshi, E. Nowak, M.T. Robson, E. Duch, M.
Farinelli, C. Wang, R.A. Conti, D.M. Canaperi, L. Deligianni, A.
Kumar, K.T. Kwietnaik, C. D'Emic, J. Ott, A.M. Young, K. W. Guarini
and M. Ieong; IBM MICROELECTRONICS; East Fishkill, N.Y.
Coffee
Break 9:40 - 9:55 A.M.
SESSION
XI - 9:55 A.M. - 12:15 P.M.
VLSI MULTILEVEL
INTERCONNECTION
VMI
PROCESS, MODEL & SIMULATION, METROLOGY
Chairman: Dr. Gregory Amico
LAM RESEARCH CORP.
San Jose, California
VMI
PROCESSING
11.A
“Interconnect Patterning in a Single Step With Multi-lever Nanoimprint
Lithography” M.D. Stewart, F. Palmieri, J. Hao, K. Jen, Y.
Nishimura and C.G. Willson; UNIV Of TEXAS; Austin, TX; J. Wetzel; ATDF;
Austin, TX; and G.M. Schmid; MOLECULAR IMPRINTS; Austin, TX.
11.B
“Etch Processing Trends for Advanced Interconnects” by P.
Loewenhardt, J. Marks and A. Athayde; LAM RESEARCH; San Jose, CA.
(Invited
Paper)
---
POSTER PAPERS ---
11.C
“A Novel SOG Coating Method to Achieve Perfect Planarization” by
S.L. Hsu, S.Y. Yang, W.Y. Lin, C.W. Dai, P.C. Yang, H.C. Hsueh, C.W.
Shiang and R.C. Yang; VANGUARD INT’L; Taiwan, R.O.C.
11.D
“Wet and Supercritical Cleans of Copper / Ultra-Low-k Structures in
Sub-65nm Device Geometries” by C.P. Hsu, B. Cruz, S. Lippy, J.
Stewart, W. Cady and J. Covington; J.T. BAKER MICRO; Phillipsburg,
N.J.
11.E
“Tungsten Via ‘Touch-Up’ by Using Argon Plasma Preclean Process”
by W.P. Chiu, C.C. Liaw, B.R. Ni, J. Chen; PROMOS TECH; Taiwan, R.O.C.
MODELING
& SIMULATIONS
11.F
“Thermal Scaling Analysis of Multilevel Copper/ Low-k Interconnect
Structures in Deep Nanometer Scale Technologies” by S. Im, K.E.
Goodson; STANFORD UNIV; Stanford, CA; and N. Srivastava, K. Banerjee;
UNIV. Of CALIFORNIA, Santa Barbara, CA.
11.G
“Buffer Insertion Location Optimization for
Post
Route Optimization”
by J.S.H.
Wang; SMART-IC TECH; Taiwan, R.O.C.
(Invited
Paper)
11.H
“Spatial Variability of Critical Dimensions” by P. Friedberg and
C.J. Spanos; UNIV. Of CALIFORNIA; Berkeley, CA.
(Invited
Paper)
11.I
“Simplification of Spatial Sturctures by Simulation With Periodic
Boundaries” by A. Nentchev, R. Sabelka and S. Selberherr; VIENNA
UNIV. TECH; Vienna, AUSTRIA.
11.J
“Model-Based Approach In Design for Yield” by A. Markosian;
PONTE SOLUTION; Mountain View, CA.
(Invited
Paper)
---
POSTER PAPERS ---
11.K
“A Fast, Exact Sum-Over-Paths Impulse-Response Moment-Extraction
Algorithm for “Giga-Coupled” RLCM IC Interconnects” by D.
Krishna, R.B. Iverson, J. Kalyanasundharam and Y.L. LeCoz; RENSSELAER
POLYTECH; Troy, NY; and D.M. Petranovic; MENTOR GRAPHICS; Wilsonville,
OR.
11.L
“A Sum-Over-Paths Impulse-Response Moment Extraction Algorithm for IC
Interconnect Networks: Verification, Coupled RLC Lines” by Y.L.
LeCoz, G. Hariharan, D. Krishna, J. Kalyanasundharam; RENSSELAER
POLYTECH; Troy, NY; and D.M. Petranovic; MENTOR GRAPHICS; Wilsonville,
OR.
--
METROLOGY --
---
POSTER PAPERS ---
11.M
“Next Generation Inspection / Metrology for 3D Integration” by R.
Kruse, M. Darwin, R. Stoner, P. de Groot, X.C. De Lega; ZYGO CORP;
Middlefield, CT.; and K. Ahmed, J. Lachance, M. Clay; SOLVISION;
Quebec, CANADA.
11.N
“Analysis of Precursor Compounds for Trace Metal Impurities by ICPMS”
by P. Clancy, S. Anderson; AIR LIQUIDE; Dallas, TX.
11.O
“Gray Level Value for Measurement for In-Line Process Control” by
J. Jau, W. Fang and H. Xiao; HERMES MICROVISION; Milpitas, CA.
2005
VMIC AWARDS LUNCHEON
Thursday, October 6; 12:15
- 1:45 P.M.
(Luncheon Presentation -
1:15 -
1:45 PM)
“PRACTICAL INTEGRATION OF
LOW-k
DIELECTRICS TO 45 nm
FOR
PRODUCT DEVELOPMENT”
Dr.
Takeshi Nogami
SONY / IBM MICROELECTRONICS
Tokyo, JAPAN
SESSION
XII
VLSI MULTILEVEL INTERCONNECTION
SELECTED
MLM TOPICS
Chairman: Dr. Willi Volksen
IBM ALMADEN RESEARCH CTR.
San Jose, California
--
BARRIERS --
12.A “Advanced Copper
Dielectric Barrier Process for 65 nm and Beyond” by J.M. Chen, T.C.
Tsai, K.C. Lai, C.C. Liu, C. Huang and S.F. Tzou; UNITED MICRO. CORP;
Taiwan, R.O.C.
(Invited
Paper)
---
POSTER PAPERS ---
12.B
“Comparative Study of Barrier Layers in Copper Interconnect for Ultra
Large Scale Integration Interconnects” by K. Wang, A.B. Horsfall, A.
O’Neill, S.J. Bull; UNIV. Of NEWCASTLE; I.O. Ladeji; A. Cuthberson; ATMEL;
Tyne, UNITED KINGDOM.
-- MLM
EQUIPMENT--
12.C
“Atmospheric Pressure Inductive Plasma Technology For Integrated Circuit
Processing” by J. Zhang, B. van den Akker, S. Selitser and C.H. Ting;
4-STATE TECH; Fremont, CA.
(Invited
Paper)
12.D
“Study of the Embedded Thermo-Couples and Manufacturing Capabilities of
High Temperature High Uniformity Heater Used for Metal Deposition Process”
by A. Sidhwa, M. Willbrand, S. Melosky, C. Spinner; ST MICRO; Phoenix,
AZ; and S. Chimni, V. Sinha, N. Narendrnath and S. Bedi; APPLIED
MATERIALS; Santa Clara, CA.
-- CONDUCTOR
CMP --
12.E
“Reactive Pads for Metal CMP” by Y. Li, J. Keleher, T. Zhang; CLARKSON
U.; Potsdam, NY.; S. Hellring; PPG; Monroeville, PA.
(Invited
Paper)
12.F
“Characterization of Copper-Hydrogen Peroxide Film Growth Kinetics” by
D. DeNardis, D.R. Yeomans, A. Philipossian; UNIV. Of ARIZONA; Tucson, AZ;
and L. Borucki; ARACA; Tucson, AZ.
12.G
“Copper Chemical Mechanical Polishing Characterization and Modeling”
by A. Guyot, O. Belmont; ST MICRO; Crolles, FRANCE; S. Kordic, M. Mellier;
PHILIPS SEMI; Crolles, FRANCE; B.Smith; FREESCALE and A. Touboul; IXL
LABS; Talence, FRANCE.
(Invited
Paper)
-- POSTER
PAPERS --
12.H “A
Study on Copper CMP Planarization and Determining ECP Thickness for Copper
Interconnect Formation at 65nm Technology Node and Beyond” by C.L.
Hsu, K.H. Lin, A. Yu, S.J. Chen, C.H. Chen, C.C. Huang; S.F. Tzou; UNITED
MICRO CORP; Taiwan, R.O.C.
12.I
“The Study of Material Removal and Scratch Population Kinetics in Copper
and Tantalum Polishing” by S. Li, J. Fletcher and C. Dowell; CABOT
MICRO-ELECTRONICS; Aurora, IL.
12.J
“Single Via Plug Damage in Tungsten CMP Dependent on Via Pattern Density”
by J.K. Lee, J.D. Jeong, S.Y. Kim, H.S. Kim; ANAM SEMI; Kyunggi,
KOREA.
12.K “A
Study of PMD WCMP Erosion Effecting on Copper Interconnect Integration”
by C.L. Hsu, A. Yu, L.Y. Fang, S.J. Chen, K.H. Lin, C.C. Huang and
S.F. Tzou; UNITED MICRO CORP; Taiwan, R.O.C.
-- CMP CLEAN
PROCESSES --
-- POSTER
PAPERS --
12.L
“Influence of Area Ventilation on Scrubber Defectivity” by A.Yohannan,
P. Carlier, H. Nguyen-Ngoc, A. Sidhwa, M. Goulding, T. Gandy; ST MICRO;
Phoenix, AZ.
12.M
“Development of a Post-CMP Cleaner for BTA-Containing High and Low pH
Barrier Slurries” by D. Peters, C. Tran, K. Bartosh and C. Watts; ATMI;
Allentown, PA.
******************************************
NOTICE TO
AUTHORS OF POSTER PAPERS
Plan to put
ALL posters for ALL SESSIONS up on Tuesday, October 4, before 9:30 am at
the location designated (Check at Conference Registration Desk). Poster
boards will be provided as indicated in author kits. Be available AT YOUR
POSTER to answer questions during Session VII (from 1:00 - 2:15 pm on
Wednesday). Plan to remove your poster on Thursday afternoon from 2 - 3
pm, October 6.