TENTH  INTERNATIONAL

 

C.M.P. PLANARIZATION

FOR ULSI MULTILEVEL INTERCONNECTION

CONFERENCE

February 23 - 25, 2005

 

 

 

Wednesday, February 23, 2005

OPENING SESSION - 8:30 A.M.

Welcoming Remarks

Dr. Thomas E. Wade, Gen. Chmn.

University of South Florida

 

SESSION I -- 8:30 A.M.

KEYNOTE ADDRESS - Part I

From a Semiconductor Manufacturers’ Perspective for Future CMP,

Where Should the Following be Targeted:

- Industry/University R & D Efforts

- Government/Consortia Funding

- CMP Vendor Developments

 

PANEL MODERATOR

Peter Singer

Editor-in-Chief

Semiconductor International

 

SEMICONDUCTOR IND. PANEL

 

 Laertis Economikos, IBM, Hopewell Jct., NY

 Mark Buehler, Intel, Hillsboro, OR

 Chris Raeder, AMD, Austin, TX

Pete Beckage, Freescale, Austin, TX          

Takeshi Nogami, Sony, Tokyo, JAPAN

 Peter Thieme, Infineon, Dresden, GERMANY

 

A brief Question & Answer period will follow formal presentations.

 

 

Coffee Break 10:30 - 10:45 AM

 

 

SESSION II - 10:45 A.M. - 12:00 P.M.

VLSI MULTILEVEL INTERCONNECTION

CMP CONSUMABLES - PART I

 

                                         Chairman:               Dr. Ara Philipossian

                                                                          UNIV. Of ARIZONA

                                                                          Tucson, Arizona

 

 

2.B “Design Rules for CMP Pad Based on Pad-Characterization and its Prototype Fabrication Using Micro Molding” by S. Lee, H. Kim and D.A. Dornfeld; UNIV. Of CALIFORNIA, Berkeley, CA.

 

2.C “Pad Conditioning and Textural Effects in Chemical Mechanical Polishing” by A.S. Lawing; ROHM & HAAS; Phoenix, AZ.  Invited Paper

 

2.D “Effect of CMP Diamond Disc Conditioner Design on Slurry Flow During CMP” by A. Philipossian, Z. Li, H. Lee; UNIV. Of ARIZONA; Tucson, AZ.; and R. Kikuma, N. Rikita, K. Nagasawa; MITSUBISHI; JAPAN. Invited Paper
 

--- POSTER PAPERS ---

 

2.E “Chemical Analysis of Copper CMP Slurries Before and After Polishing for Defect Reduction” by F. Odeh, K. Cheemalapati, V.R. Duvvuru, D.K.  Bundi, S. Dhane and Y. Li; CLARKSON UNIV.; Potsdam, N.Y.

 

2.F “Cermet Ceramic Coating of Diamond Dresser for In-Situ Dressing of Chemical Mechanical Planarization” by J.C.M. Sung and K. Kan; KINIK; Taiwan, R.O.C.

 

2.G “Filled Polyurethane Pad for Chemical Mech-anical Polishing” by G. Wu, P. Galvez, S. Kirtley, T. West; THOMAS WEST; Sunnyvale, CA.

 

2.H  “Characterization of a Copper CMP Slurry” by R.K. Singh, C. Patel; MYKROLIS; Billerica, MA.; B.R. Roberts; BOC EDWARDS; Santa Clara, CA.; and R. Viscomi; CABOT MICRO; Phoenix, AZ.

 

 Box Lunches - 12:00 - 1:00 P.M.

Visit Industrial Exhibition/Poster Presentations

 

 

 

 

 

SESSION III - 1:00 - 3:00 P.M.

VLSI MULTILEVEL INTERCONNECTION

CMP PROCESS MONITORING & CONTROL

 

   Chairman:               Dr. Norm Gitis

                                   FOR TRIBOLOGY

                                                           Campbell, California

 

3.A “Measurements of Interfacial Fluid Pressure, Temperature and Tilt During CMP” by A. Osorno, I. Yoon, S.H. Ng and S. Danyluk; GEORGIA INST. Of TECH.; Atlanta, GA.

 

3.B “Analysis of Particle Flow During CMP Process Using Particle Image Velocimetry” by Y.H. Koh, H. Kim, B.U. Yoon, C. Hong, H. Cho and J.T. Moon; SAMSUNG; Yougeen, SOUTH KOREA;  and S. Shin, M. Kim and Y. Yoon; SEOUL UNIV.; Seoul, SOUTH KOREA.

 

3.C “CMP Consumables Characterization” by M. Vinogradov, N. Gitis, S. Kuiry; CTR. For TRIBOLOGY; Campbell, CA..

 

3.D “Particulate Flow Tribological Issues During CMP of Nanostructures” by C. F. Higgs III, E. Terrell, J Garcia; CARNEGIE MELLON UNIV.; Pittsburg, PA. Invited Paper

 

3.E “Instantanous, High Resolution, In-Situ Imaging of Slurry Film Thickness During CMP” by C. Gray, D. Apone, C. Rogers and V. Manno; TUFTS UNIV.; Medford, MA.; C. Barns, M. Moinpour; INTEL CORP; Santa Clara, CA.; S. Anjur; CABOT MICRO.; Aurora, IL.; and A. Philipossian; UNIV. Of ARIZONA; Tucson, AZ.

 

3.F “Measurement and Control of Slurry Film Thickness and Wafer Surface Temperature in CMP” by G.P. Muldowney, J. J. Hendron; ROHM & HAAS; Newark, DE.
 

--- POSTER PAPERS ---

 

3.G “CMP Process Evaluation With PadProbe^TM” by S. Hosali, E.Busch; SEMATECH; Austin, TX.; and M. Vinogradov, N. Gitis; CENTER for TRIBOLOGY; Campbell, CA.

 

3.H “Friction Force Monitoring System in CMP Process” by H. Jeong, B. Park, H. Lee, H. Kim, H. Seo, G. Kim and K. Park; PUSAN NAT’L UNIV.; Pusan, KOREA; and M. Kinoshita, J. Park; NITTA HAAS; Nara, JAPAN.

 

3.I “Use of Segmented Algorithm to Improve Endpoint Repeatability for Copper CMP” by E. Labelle and R. Carpio; ATDF; Austin, TX.

 

3.J   “Erosion Characterization and Process Control in Copper CMP Process” by S. Lee, Z.Liu, C. Saravanan, J. Hu and R. Korlahalli; NANO-METRICS; Milpitas, CA.

 

Coffee Break  3:00 - 3:15  PM

 

 

SESSION IV - 3:15 - 5:00 P.M.

VLSI MULTILEVEL INTERCONNECTION

 C.M.P.  MODELING & SIMULATION - PART I

 

                                          Chairman:              Dr. Mike Fury

                                                                         DUPONT EKC TECH.

                                                                         Hayward, California

 

4.A “Applications of Full-Chip CMP Modeling: Copper, STI and Beyond” by T. Smith, D. White and R. Moore; PRAESAGUS; San Jose, CA. Invited Paper

 

4.B “A Pad Wear Model for CMP Process Optimization” T.P. Merchant, J.N. Zabasajja; FREESCALE SEMI; Tempe, AZ.; L.J. Borucki; INTELLIGENT PLANAR; Mesa, AZ.; and A. S. Lawing; ROHM & HAAS; Phoenix, AZ.

 

4.C “Accurate 3-D Capacitance Test and Character-ization of Dummy Metal Fills to Achieve Design for Manufacturability” by K. J. Chang, D.C.H. Lyu; TSING HUA UNIV.; Taiwan, R.O.C.; and Y.C. Chiu, E. Chang and L. Chen; UNITED MICRO. CORP; Taiwan, R.O.C.

 

4.D “Optimization of CMP Pad Groove Arrays for Improved Slurry Transport, Wafer Profile Correction and Defectivity Reduction” by G.P. Muldowney; ROHM & HAAS; Newark, DE.

 

4.E “Flash Heating in Chemical-Mechanical Polishing” by L. Borucki; INTELLIGENT PLANAR; Mesa, AZ.; and J. Sorooshian, Z. Li, Y. Zhang and A. Philipossian; UNIV. Of ARIZONA; Tucson, AZ.

--- POSTER PAPERS ---

 

4.F  “Synergy Between Chemical Dissolution and Mechanical Abrasion During Chemical Mechanical Polishing of Copper” by W. Che, A. Bastawros and A. Chandra; IOWA STATE UNIV.; Ames, IA.

 

4.G “The Multi-Product Oxide CMP Mixing Process Control by Auto Feedback System” by Y. Hung, A. Su and M. C. Yang; PROMOS TECH.; Taiwan, R.O.C.

 

4.H  “A Theoretical Study on the Relationship Be-tween Wafer Surface Pressure and Wafer Backside Loading in CMP” by G. Fu; LAM RESEARCH; Fremont, CA.; and A. Chandra; IOWA STATE UNIV.; Ames, IA.

 

Thursday, February 24, 2005

 

SESSION V  --  8:00 A.M.

KEYNOTE ADDRESS - Part II

From a Vendor / Marketing Consultants Perspective for Future CMP,

Where Should the Following be Targeted:

       - Industry/University R & D Efforts

       - Government/Consortia Funding

       - CMP Vendor Developments

 

PANEL MODERATOR

Peter Singer

Editor-in-Chief

Semiconductor International

 

VENDOR / MKT.  PANEL

 

Cathie Markham, VP Tech., Rohm & Haas

Cliff Spiro,VP Res., Cabot Microelectronics

  Robert Castellano, Pres., Information Network

 

A brief Question & Answer Period will follow formal presentations.

        

Coffee Break  - 9:15 A.M. - 9:30 A.M.

 

 

SESSION VI  - 9:30 A.M. - 12:30 P.M.

VLSI MULTILEVEL INTERCONNECTION

CMP PROCESS CHARACTERIZATION

& POST-CLEANING PROCESSES

 

                                                Chairman                   Dr. Mansour Moinpour

                                                                                   INTEL CORP.

                                                                                   Santa Clara, California

 

CMP PROCESS CHARACTERIZATION

 

6.A “eCMP and Its Application to 65 nm Node Integration” by A. Sakamoto; SONY; Tokyo, JAPAN; and L. Economikos, IBM MICRO; Hopewell Junction, N.Y. Invited Paper

 

6.B “Use of an Electrochemical Quartz Crystal Micro-balance to Elucidate the Adsorption of Glycine and Hydrogen Peroxide on Copper Surfaces” by  L.Wang, F. Doyle, UNIV.  CALIF; Berkeley, CA. Invited Paper

 

6.C “Dielectric and Copper CMP, the Evolution of Integrated Process Control and Solutions Down to  65 nm and Below” by G. Dishon, M. Finarov and A. Ger; NOVA  INST.; Rehovoth, ISRAEL. Invited Paper

 

6.D  “Manipulation Effects in Chemical-Mechanical Polishing” by H. Liang and M. Kulkami; TEXAS A & M UNIV.; College Station, TX.; J. Johnson and A. Zinovev; ARGONNE NAT’L LAB; Argonne, IL. Invited Paper
 

--- POSTER PAPERS ---

 

6.E “Effect of Slurry Temperature and Flow Rate on Material Removal In Chemical Mechanical Polishing Process” by H. Kim,  S. Lee, J. Choi and D. Dornfeld; UNIV. Of CALIFORNIA; Berkeley, CA.; and H. Jeong; PUSAN UNIV.;  KOREA.

 

 

CMP POST-CLEANING PROCESSES

 

6.F “Advanced Post CMP Cleaners for Copper Damascene Processes” by E. Kneer; FUJIFILM; Queen Creek, AZ.

 

6.G “A Non-BTA Based Novel Post CMP Clean Solution” by J. Zhao, D.K. Bundi, K. Cheemalapati, V.R. Duvvuru and Y. Li; CLARKSON UNIV.; Potsdam, N.Y. Invited Paper

 

6.H “New Cleaning Process of Copper Contaminated by the CMP at the Surface of Low-k Interlayers” by T. Hara, HOSEI UNIV.; Tokyo, JAPAN and K. Kinoshita; SEZ AG; Villach, AUSTRIA; S. Balakumar; INST. Of MICROELECTRONICS; SINGAPORE. Invited Paper

 

6.I  “Experimental and Modeling Study of Submicron Particle Removal from Deep Trenches” by K. Bakhtari, R.O. Guldiken and A.A. Busnaina; NORTHEASTERN UNIV.; Boston, MA.; J.G. Park; HANYANG UNIV.; Ansan, KOREA. Invited Paper

 

6.J   “Advancements in Post Copper CMP Cleaning Solutions” by C. Shang, D. Frey, D. Maloney; EKC TECH; Hayward, CA.; K. Matsumoto; EKC TECH; Kawasaki, JAPAN.Invited Paper
     

--- POSTER PAPERS ---

 

6.K “Post CMP Cleaning of Dielectric Surfaces” by H. Liu, H. Goodman, B. Santora, D. Merricks and B. Her; FERRO CORP; Penn Yan, N.Y.

 

6.L “An Investigation of Shelf Life on the Service Life of the DNS AS-2000 Double-Side Brush Chamber Brushes” by M.K.M. Fei, P.C. Siong and N.T. Leong; S.S.M.C.; SINGAPORE.

 

6.M “Device Failure Mechanism Through Particle Adhesion” by G.S. Cho, H.S. Kim, J.K. Lee, J.D. Jeong, D.Y. Kim, Y.W. Lee, H.P.Kim, H.S. Jeong,H.W. Ha, W.S. Yang; ANAM SEMI.; Kyunggi, KOREA.

 

6.N   “Effect of Barrier Slurry Properties on Post-CMP Cleaning Efficacy” by D. Peters, K. Bartosh, C. Watts and C. Tran; ATMI; Allentown, PA.

 

Thursday Lunch on Your Own

Not Provided by Conference

 

SESSION VII - 1:15 P.M. - 2:30 P.M.

VLSI MULTILEVEL INTERCONNECTION

DEDICATED TIME FOR CMPPOSTER  PAPERS,  EXHIBIT VIEWING

 

 

SESSION VIII - 2:30 P.M. - 5:45 P.M.

VLSI MULTILEVEL INTERCONNECTION

C.M.P. CONDUCTOR & DIELECTRIC PROCESSES

 

                                                                                    Chairman:                     Dr. David Dornfeld

                                                                                UNIVERSITY OF CALIFORNIA

                                                                                Berkeley, California

 

CMP CONDUCTOR PROCESSES

 

8.A “Stress-Free Copper Planarization Using A Modified Electrochemical System” by J. Huo and J. McAndrew; AIR LIQUIDE; Countryside, IL.

 

8.B “Effect of Hydrogen Peroxide on Frictional and Thermal Characteristics During Copper CMP” by J.G. Park, H. Eom; HANYANG  UNIV; KOREA. Invited Paper

 

8.C “Competative Surface Adsorption of Key Chemi-cals on Abrasive Particles in Copper CMP Slurry”  by S.K. Govindaswamy, F. Odeh, S. Dhane and Y.  Li; CLARKSON UNIV.; Potsdam, N.Y.

 

8.D  “Novel Low-Abrasive Slurries and Abrasive-Free Solutions for Copper CMP” by I. Belov, J.Y. Kim, T. Moser, K. Pierce; PRAXAIR; Indianapolis, IN.

 

--- POSTER PAPERS ---

 

8.E “Adjusting Copper Surface Roughness for Optimal Performance” by C.L. Hsu, W.C. Su; PROMOS; Taiwan, R.O.C.; and Q.C. Ye, T. Thomas, R. Lavoie and C.F. Dai; ROHM & HAAS; Newark, DE.

 

8.F  “Chemical Inert Tungsten Particle in a Tungsten CMP Process” by L.H. Whye, A. Tan, R. Soh, T.C. Yong, C.K. Wei, C.C. Peng, N.T. Leong. W.F. Inn; S.S.M.C.; SINGAPORE.

 

8.G “Copper Removal Rate Control in Chemical Mechanical Polishing of Barrier Materials” by Z. Liu and R. Schmidt; ROHM & HAAS; Newark, DE.

 

CMP STI & DIELECTRIC PROCESSES

 

8.H “Polishing Performance of CeO₂ Base Slurry and Surfactant on STI Structure Wafers” by P.H. Sun, Y.C. Chen, K.T. Liao, T.H. Yu; WINBOND; Taiwan, R.O.C. Invited Paper

 

8.I “Investigation of Ceria-Silica Interactions During STI Polishing” by J. Abiade, S. Jung; UNIV. Of FLORIDA; Gainesville, FL.; and R.K. Singh: UNIV. Of TEXAS; Austin, TX. Invited Paper

 

8.J “STI CMP Scratch Reduction by Slurry Improvements: Additive & Abrasive Control & Optimization” by J.H. So, D.J. Lee, N.S. Kim, K.M. Kang, S.M. Chun; SAMSUNG; Youngin, KOREA; and S.M. Yang; KOREA INST. Of SCIENCE & TECH; Daejeon, KOREA. Invited Paper

 

8.K “Process Development on a Hybrid Fixed Abra-sive STI CMP for Logic Applications at 65 nm Technology Node”by T.C. Tsai, N. Chen, S.K. Chu, C.H. Chen, C. Huang and S.F. Tzou; UNITED MICROELECTRONICS CORP; Taiwan, R.O.C. Invited Paper

 

8.L “Effects of Abrasive Size and Surfactant Concentration in Ceria Slurry for Shallow Trench Isolation CMP” by H.S. Park, J.G. Jung, J.Y. Park, J.H. Shin, C.H. Ryu, H.C. Sohn; HYNIX SEMI; Kyunggi, KOREA; H.G. Kang, T. Katho and J.G. Park; HANYANG UNIV.; Seoul, KOREA.

 

8.M “Fumed Ceria for Use in ILD and STI CMP” by M. Kroll, W. Lortz; DEGUSSA; Hanau, GERMANY; R. Brandes; DEGUSSA; Piscataway, N.J.; and A. Philipossian; UNIV. Of ARIZONA; Tucson, AZ.

 

-- POSTER PAPERS --

 

8.N “Recent Advances in Ceria-Based Slurries for STI and ILD Applications” by B. Her, D. Merricks and B. Santora; FERRO; Penn Yan, N.Y.

 

8.O  “CMP Performance of NF₃ Added SiO ₂ Film Using Two Kind of Slurries” by J.H. Kim, H. Lee, H.J. An, Y.H. Yoon, H.H. Kim, E.R. Hwang, S.H. Pyi, B.H. Choi, J.W. Kim and S.W. Park; HYNIX SEMI; Kyungki, KOREA.

 

-- LATE NEWS PAPER --

 

8.P  “A Method of Reducing the Effect of Heat on the Spindle Pressure Regulators in the Applied Materials Mirra Polisher” by M.K.M. Fei, H.S. Hyun, N.T. Leong, P.C. Siong, L.T. Wei, L.K. Fai. K.C. Chyan and P.Y.K. Hoe; S.S.M.C.; SINGAPORE.

 

Friday, February 25, 2005

SESSION IX - 8:00 A.M. - 9:20 A.M.

VLSI MULTILEVEL INTERCONNECTION

CMP INSTRUMENTATION & HARDWARE

 

                                                                              Chairman:              Dr. David Hansen

                                                                      NOVELLUS CORP.

                                                                       San Jose, California

           

9.A “Wide Area AFM With Digital Probing Method for CMP Process Evaluation” by H. Koyabu; HITACHI; Tokyo, JAPAN; Y. Kembo; HITACHI; Tsuchiura, JAPAN; S. Hosaka; GUNMA UNIV.; Gunma, JAPAN.

 

9.B   “Precision Point-of-Use Blending for CMP and Post-CMP Cleaning Chemicals” by D.J. Albrecht; ENTEGRIS; Minneapolis, MN.

 

9.C “In-Situ Acoustic Emission Monitoring of Surface Chemical Reactions for Copper CMP” by J. Choi, D.E. Lee and D.A. Dornfeld; UNIV. Of CALI-FORNIA; Berkeley, CA.

 

9.D   “CMP and PiezoChuck” by V. Galazky; IGAM ENGR; Barleben, GERMANY.

 

-- POSTER PAPERS --

 

9.E   “Shear Force Study of Low-k / Copper CMP For 65 nm Generation and Beyond” by L.G. Chen, H.H. Lu, W.C. Chiou, Y.H. Chen, S.M. Jeng, S.M. Jang, C.H. Yu and M.S. Liang; T.S.M.C.; Taiwan, R.O.C.

 

9.F  “The Advantage of the NIR Spectral Range in Implementation of CLC for a Poly CMP Process” by R. Alon, A. Ger; NOVA MEAS. INST; Rehovoth, ISRAEL.

 

Coffee Break 9:20 A.M. - 9:35 A.M.

 

SESSION X - 9:35 A.M. - 12:00 P.M.

VLSI MULTILEVEL INTERCONNECTION

C.M.P. CONSUMABLES Part II

 

                                                Chairman:              Dr. Paul Feeney

                                                                               CABOT MICRO.

                                                                               Aurora, Illinois

 

10.A “The Effect of Pad Topography on Surface Non-Uniformity in Copper CMP” by K. Noh, K. Kopanski, N. Saka and J.H. Chun; M.I.T.; Cambridge, MA.

 

10.B “Break-In Pad Surface Analysis With FT-IR and Raman Scattering Spectroscopy” by T. Fujita, O. Kinoshita; SEIMITSU; Tokyo, JAPAN; M.Ishikura, N. Kawai, Y. Morioka; NITTA HAAS; Tokyo, JAPAN.

 

10.C “Fujimi Next Generation Tungsten CMP Slurry” by P. Lefevre, K. Sakai, K. Ohno, K. Tamai and K. Ina; FUJIMI; Tualatin, OR.

 

10.D “Direct Wafer Polishing With 5 nm Diamond” by J.C.M. Sung and M.F. Tai; KINIK; Taiwan, R.O.C.

 

10.E “Advanced Barrier Slurries for 65 nm and 45 nm Technology Nodes” by A. Zutshi; DUPONT NANOMAT’L’; Hayward, CA. Invited Paper

 

10.F “The Effect of Ceria Slurry pH and Hersey Number on CMP of Silicon Dioxide” by J.H. Lim, S.K. Yun, J.D. Lee, B.U. Yoon, C. Hong, H.K. Cho and J.T. Moon; SAMSUNG; Gyeonggi, KOREA.

 

10.G “The Evolution of IC 1000^TM in CMP” by D. Chambers and H. Rayle; ROHM & HAAS; Newark, DE.
 

--- POSTER PAPERS ---

 

10.H “A Study of a Centipede Pad Dresser With Individual Controllable Leveling of Single Diamond Grits in Break-In Process” by Y.L. Pai, C.C. Teng, M.H. Chan, S.C. Huang; KINIK; Taiwan, R.O.C.

 

10.I “Politex Prima Pad: Continuous Improvement on Industry Standard Material” by K.S. White, N. Chechik, H. Sanford-Crane; ROHM & HAAS; Newark, DE.

 

10.J “A Novel Rotary Pad Material for Improved Lifetime in Copper CMP” by D. Lamb, C. Forrestal, K. Pierce; PRAXAIR; Indianapolis, IN.; J. Cianciolo, T. Dunn, C. Galloway; PRAXAIR; Salem, NH.

 

10.K  “A Study on the Cutting Phenomena of the Pad Used in CMP Process by Single Diamond Grit” by C.C. Teng; KINIK; Y.S. Liao, H.W. Chou; NAT’L TAIWAN UNIV; Taiwan, R.O.C.

 

10.L “The Characterization of Polyurethane Elastomer Pad With New Concept of Micro-Hole & Wave Groove on its Surface” by J.C. Yang, D.W. Kim, S.M. Cheon, J.D. Kim, S.H. Ryu; SAMSUNG; Gyeonggi, KOREA; J. Kim,  J.Y. Lee, I.H. Park; SKC CHEMICAL; Chungbuk, KOREA.

 

 

CMP-MIC LUNCHEON - 12:15 - 2:00 P.M.

 

“ CAN SIX SIGMA WORK IN A

FAST MOVING CMP INDUSTRY ? ”

Cliff Spiro

Vice President for Research & Development

Adam Weisman, VP Operations

Julie Hensel, Director QC

CABOT MICROELECTRONICS CORP.

Aurora, Illinois

 

 

 

SESSION XI - 2:00 P.M. - 4:00 P.M.

VLSI MULTILEVEL INTERCONNECTION

C.M.P. APPLICATIONS & RELIABILITY

 

                                          Chairman:                Dr. Peter Burke

                                                                           LSI Logic

                                                                           Santa Clara, California

 

CMP APPLICATIONS

 

11.A “Carbon Nanotube Vias for Multilevel Interconnects Using CMP Techniques” by M. Nihei, A. Kawabata, S. Sato, D. Kondo, M. Horibe, H. Shioya, T. Iwai and Y. Awano; FUJITSU; Atsugi, JAPAN. Invited Paper

 

11.B “Chemical Mechanical Polishing - A Key Enabling Technology for Tight Pitch 3-D Memory Integration” by V. Dunton and S. Sivaram; MATRIX SEMI; Santa Clara, CA. Invited Paper

 

11.C “Innovation in Traditional CMP Applications” by P. Feeney, R. Vacassy, A. Walters and S. Anjur; CABOT MICRO; Aurora, IL. Invited Paper

 

11.D “Integration of CMP Into a 3-D Memory Process” by V. Dunton; MATRIX SEMI.; Santa Clara, CA.

 

--- POSTER PAPERS ---

 

11.E “Accurate Characterization of Flash Memory Cell Capacitance for Optimal Sub-100 nm Embedded Flash Memory Process Design” by J.S. Wang, K.J. Chang; eMEMORY TECH.; Taiwan, R.O.C.

 

11.F  “Development of a New Tungsten Polishing Pad Utilizing Outsource CMP Capabilities” by R.L. Rhoades; TOTAL FAB SOLN’S; Tempe, AZ.; and J. Bare, A.J. Clark and E. Atkinson; PSILOQUEST; Orlando, FL.

 

 

CMP RELIABILITY ISSUES

 

11.G “Study on the Degradation of the TDDB Reliability of Copper / Low-k Interconnects Caused by Copper CMP Process” by Y. Yamada, N. Konishi, S. Watanabe, J. Noguchi, T. Jimbo and O. Inoue; HITACHI; Tokyo, JAPAN. Invited Paper

 

11.H “Failure Analysis and Characterization Methods for Copper CMP” by S. Kordic, L.F.T.z. Kwakman, M. de la Bardonnie, A. Berthoud; PHILIPS SEMI.; F. Lorut, S. Petitdidier, S. Courtas, C. Wyon, C. Trouiller; ST MICRO; K. Ly, M. Zaleski, B. Smith; FREESCALE; Crolles, FRANCE. Invited Paper
 

--- POSTER PAPERS –

 

11.I  “Controlling 854 Product Defectivity Prior to and During Copper and Barrier CMP” by R.Carpio, G. Kenig, F. Tolic, T. Alzaben, D. Sheu and D. Miller; ATDF; Austin, TX.; and J. Ngyuen; ROHM & HAAS; Phoenix, AZ.

 

11.J “Design of Diamond Conditioner for Preventing Diamond Pull Out” by J.F. Jiang, J. Tsay, Y.J. You, and S.N. Peng; T.S.M.C.;Tiawan, R.O.C.;  P. Kim; E. Jan; SHINHAN DIAMOND; SOUTH KOREA.

 

NOTICE TO AUTHORS

OF POSTER PAPERS

 

Plan to put ALL posters for ALL SESSIONS up on Wednesday, February 23, before 9:30 am at the location designated (Check at Conference Registration Desk). Poster boards will be provided as indicated in author kits. Be available AT YOUR POSTER  to answer questions during Session VII (from 1 - 2:30 pm on Thursday, Feb. 24).  Plan to remove your poster on Friday afternoon from 3 - 4 pm. All posters are to be down for room clean-up by 4 pm on Friday, February 25.