VLSI MULTILEVEL INTERCONNECTION
STATE-OF-THE-ART
SEMINAR
Wednesday, September 29, 2004
This year’s state-of-the-art SEMINAR will address those issues associated with current fundamental developments in advancing VLSI/ULSI multilevel interconnection towards greater functionality, density and speed. It will include a review and discussion of those primary topical areas which impact today's multilevel interconnection event as well as project future direction for this critical industry. A distinguished set of lecturers will participate in this SEMINAR, which is a MUST for all engineers, managers and technicians working on VLSI/ULSI multilevel interconnection. The registration fee includes coffee breaks, luncheon and a visuals booklet. THIS COURSE HAS LIMITED ENROLLMENT. YOU ARE ENCOURAGED TO ADVANCE REGISTER EARLY.
TOPICAL COVERAGE
I. INTRODUCTORY REMARKS
Dr. Thomas E. Wade
Seminar Chairman
University of South Florida
II. ULSI
CHALLENGES: NANOMETER SCALE INTERCONNECT
CHALLENGES
Dr. Kaustav Banerjee
University of California
Santa Barbara, California
III. DIELECTRICS:
LOW-k & ULTRA LOW-k
POROUS DIELECTRICS
Dr. Willi Volksen
IBM Almaden Research Center
San Jose, California
IV. COPPER BARRIERS:
ULTRA THIN TRANSITION METAL
ADVANCE BARRIERS FOR COPPER
METALLIZATION
Dr. Ravi K. Laxman
ATMI Advanced Materials
Bethlehem, Pennsylvania
Seminar Luncheon
“CVD LOW-k / COPPER METALLIZATION FOR 90
NANOMETERS AND CHIP PACKAGE INTERACTIONS”
Dr. Hazara Rathore
IBM MICROELECTRONICS
New Hope Junction, New York
V. RELIABILITY ISSUES:
TRENDS IN ELECTROMIGRATION OF
65 nm TECHNOLOGY & BEYOND
Dr. Young-Joon Park
Texas Instruments
Dallas, Texas
VI. BEOL DIELECTRICS:
ULSI BACK-END-OF-THE LINE
DIELECTRIC DEVELOPMENTS
Dr. Devendra Kumar
ASM Corporation
San Jose, California
VIII. 3-D INTEGRATED CKTS:
WAFER-LEVEL 3D INTEGRATED CKTS: AN
ALTERNATIVE TO SoCs & SiPs?
Dr. Ronald Gutmann
Rensselaer Polytechnical Institute
Troy, New York
IX. CLOSING REMARKS