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TWENTY
FIRST INTERNATIONAL
VLSI MULTILEVEL INTERCONNECTION
CONFERENCE
September 30 - October 2, 2004
ADVANCE PROGRAM
Thursday,
September 30, 2004
OPENING SESSION --- 9 A.M.
Welcoming
Remarks by the General Chairman
Dr. Thomas E. Wade
University
of South Florida
SESSION I --- 9:15 A.M.
KEYNOTE ADDRESS
“TRADING FABS FOR FOCUS -
NEW DIRECTIONS IN R & D”
Dr. Siva Sivaram
Chief
Operational Officer
MATRIX
SEMICONDUCTOR
Santa Clara,
California
Coffee Break 9:45 - 10:00
A.M.
SESSION II
- 10:00 A.M. - 12:15 P.M.
VLSI MULTILEVEL INTERCONNECTION
CONDUCTOR SYSTEMS
Chairman:
Dr.
Willi Volksen
IBM ALMADEN RES.
CENTER
San
Jose, California
2.A
“Barrier / Copper Direct Deposition Possibility Using Supercritical Carbon
Dioxide” by E. Kondoh; UNIVERSITY OF YAMANASHI; Tokyo, JAPAN.
(Invited
Paper)
2.B
“Integration of Tungsten Damascene as True First Metal in a 130 nm Flash
Technology” by S. Louwers, V. Beugin, S. Chanaud, R. Coppard, S.
Delbert and Y. Huiban; ATMEL; Rousset, FRANCE.
2.C
“Copper Interconnection Fabrication by Displacing the Pre-Patterned SiC
Barrier Thin Film” by C.H. Yang and W.L. Yang; FENG CHIA UNIVERSITY;
Taiwan, REPUBLIC OF CHINA.
2.D
“CoWP Capping Process for Copper Damascene Interconnection” by T.
Hara HOSEI UNIVERSITY; Tokyo, JAPAN; K. Kinoshita; SEZ; Villach,
AUSTRALIA; and S. Balakumar; INST. OF MICROELECTRONICS; SINGAPORE.
(Invited
Paper)
2.E
“Enhancement of Adhesion Strength of Copper Layer With Low Dielectric
Constant Liners in Copper Interconnects” by S. Balakumar, S.C. Hwee
and R. Kumar; INST. OF MICROELECTRONICS; SINGAPORE; G. Wang; UNIVERSITY OF
SINGAPORE; and T. Hara; HOSEI UNIVERSITY, Tokyo, JAPAN.
2.F
“Reliability of Copper Interconnects With CVD Low-k BEOL Dielectric for 90
nm CMOS Technology” by H. Rathore; IBM MICRO-ELECTRONICS; Hopewell
Junction, N.Y.
(Invited Paper)
2.G
“Electroplated Copper Films Using a Mixture of CuSO4 and CuSiF
6 as Electrolytes” by Y.L. Wu; NATIONAL CHI-NAN UNIVERSITY;
Taiwan, R.O.C.; C.S. Cheng and H. L. Hwang; NATIONAL TSING-HUA UNIVERSITY;
Taiwan, R.O.C.
--- POSTER PAPERS---
2.H
“Barrier Capability of NbNx Films Deposited by Different Nitrogen Flow
Rate Against Copper Diffusion in Cu / NbNx / n+- p Junction
Diodes” by F. C. Jiang, W. L. Yang, T. K. Kang and F. T. Chien; FENG
CHIA UNIVERSITY; Taiwan, R.O.C.; W.F. Wu; NATIONAL NANO DEVICE LAB;
Taiwan, R.O.C.; and C. C. Yeh; NATIONAL TSING HUA UNIVERSITY; Taiwan,
R.O.C.
2.I
“Recess Etching Process for Copper Damascene Interconnections Employing
Spin Etching Process” by K. Kinoshita; SEZ; Villach, AUSTRALIA ;T.
Hara HOSEI UNIVERSITY; Tokyo, JAPAN and S. Balakumar; INST. OF
MICROELECTRONICS; SINGAPORE
(Invited Session)
SESSION
III - 1:30 - 3:10 P.M.
VLSI MULTILEVEL INTERCONNECTION
THREE DIMENSIONAL SYSTEMS
Chairman:
Dr. John F. McDonald
RENSSELAER POLYTECHNIC INST.
Troy, New York
3.A
“Electrical Integrity of MOS Devices in Laser Annealed Three Dimensional
Integrated Circuit Structures” by B. Rajendran, R. S. Shenoy, M. O.
Thompson and R.F.W. Pease; STANFORD UNI-VERSITY; Stanford, CA.; M.
Thompson; CORNELL UNIVERSITY; Ithaca, N.Y.
(Invited Paper)
3.B “A
Three Dimensional Interconnect Methodology Applied to iA32-Class
Architectures for Performance Improvement Through RC Mitigation” by D.
W. Nelson, C. Webb, D. McCauley, K. Raol, J. Rupley, J. DeVale and B.
Black; INTEL CORP; Hillsboro, OR.
3.C “A
Wafer Bonding Approach for Three Dimensional Processor Memory Chip -
Stacks”by J. F. McDonald, R. P. Kraft, P. Belemjian, O. Erdogan, R. R.
Gutmann, J. Q. Lu, A.Y. Zeng and K. Rose; RENSSELAER POLYTECH INST.; Troy,
N.Y.; C. A. Maier; AMD; Sunnyvale, CA.
(Invited Paper)
3.D
“Techniques for Producing Three Dimensional Integrated Circuits With High
Density Interconnect” by R. Patti, M. Hilbert, S. Gupta, S. Hong;
TEZZARON SEMICONDUCTOR; Naperville, IL.
3.E
“Wafer Level Three Dimensional LSI Technology” by M. Koyanagi and H.
Kurino; TOHOKU UNIVERSITY; Tokyo, JAPAN.
(Invited Paper)
Coffee Break 3:10 -
3:25 P.M.
SESSION IV
- 3:25 - 5:00 P.M.
VLSI MULTILEVEL INTERCONNECTION
CMP PROCESS DEVELOPMENT I
Chairman:
Dr. Ronald R. Gutmann
RENSSELAER POLYTECHNIC INST.
Troy, New York
4.A
“Damascene Cu / Low-k CMP Process Limits Derived From AFM and Electrical
Measurements” by R. W. Donis, D. T. Price and J. Kalpathy-Cramer; LSI
LOGIC; Gresham, OR.
4.B
“Rinsing and Drying Issues Related to Post CMP Cleaning Process” by W.
Fyen, K. Xu, J. V. Steenberger, G. Vereecke, R. Vos, S. Arnauts, J. Rip,
K. Kenis, F. Holsteyns, D. Hellin, G. Doumen and W. Mertens; IMEC; Leuven,
BELGIUM; H. Kraus; SEZ; Villach, AUSTRIA; K. Lee; SAMSUNG; Gyeonggi, KOREA
(Invited)
4.C “In
- Situ Friction Characterization During Copper Chemical Mechanical
Planarization” by P. Leduc; CEA-LETI; Grenoble, FRANCE; M. Savoye, D.
Scevola, M. Rivoire; CROLLE 2 ALLIANCE; Crolles, FRANCE.
4.D
“Improvement of Copper CMP Performance by Controlling Pad Temperature
Using Solo Pad” by T. Yokoyama, T. Komiyama, T. Fukui, T. Yamazaki, A.
Yamane and A. Isobe; ACCRETECH; Tokyo, JAPAN.
--- POSTER PAPERS ---
4.E
“Significant Improvement of Defect in CMP Process by Using Lower Retainer
Ring Pressure” by O. Kinoshita, T. Yamazaki and A. Isobe; TOKYO
SEIMITSU; Tokyo, JAPAN.
4.F
“Optimized Cleaning Processes for Direct STI Ceria Slurry CMP” by Y.
Epshteyn, A. S. Lawing, B. Mueller, J. Federowicz; ROHN AND HASS; Phoenix,
AR.; C. Tran; ATMI; Allentown, PA.
Friday,
October 1, 2004
SESSION V
- 8:45 - 10:40 A.M.
VLSI MULTILEVEL INTERCONNECTION
RELIABILITY ISSUES I
Chairman:
Dr. Young-Joon Park
TEXAS INSTRUMENTS
Dallas, Texas
5.A
“Quantitative Control of Plasma - Surface Interactions for Highly Reliable
Interconnects” by K. Yatsuda and T. Tatsumi; SONY; Tokyo, JAPAN.
(Invited
Paper)
5.B
“Bottom-Up Electroless Copper Plating Technology for ULSI
Interconnections” by S. Shingubara, Z. Wang, O. Yaegashi, T. Hao and
R. Obata; HIROSHIMA UNIVERSITY; Hiroshima, JAPAN.
(Invited Paper)
5.C
“Characterization of the Back Side Metallization Process to Minimize Warp
on the Wafers” by J. Degraffenreid, M. Goulding, R. Nickell, T. Gandy
and A. Sidhwa; ST MICROELECTRONICS; Phoenix, AZ.
5.D
“Defectivity Determination and Reduction for the CON-TACT Process” R.
Rich, B. Bartilson, J. Dachsteiner, M. Daffron, S. Gibbons, K. Marler, S.
Scott and J. Snook; BREWER SCIENCE; Rolla, MO.
5.E
“Reduction in Interconnect Clean Defects Increases Line Yield” by C.
Hatcher, K. Mortensen, R. Lappan, J. Prasad; AMI SEMICONDUCTOR; Pocatello,
ID.; C. Meuchel; SEMITOOL; Kalispell, MO.
5.F
“The Impact from Titanium Under Layer Film Thickness and the Thermal
Stress Generating Abnormal Aluminum Grains and Partial Voids in the Metal
- 1 Interconnect Lines” by C. Consalvo, M. Sacchi, A. Privitera and A.
Sidhwa; ST MICROELECTRONICS; Phoenix, AZ.
--- POSTER
PAPERS ---
5.G
“Charge to Breakdown Investigation of Gate Oxide With Different Substrate
in Dual Gate Oxide CMOS Process” by Y. Zhao, X. Xu; NEC ELECTRONICS;
Shanghai, CHINA; X. Wan; SHANGHAI IC R&D CTR.; Shanghai, CHINA.
5.H
“The Influence of Oxygen on the Contact Barrier and the Tungsten Plug
Process Post Rapid Thermal Anneal Step” by M. Gonsalves, X. Breurec,
A. Sidhwa, M. Goulding, R. Piotrowski, T. Gandy; ST MICROELECTRONICS;
Phoenix, AZ.
5.I
“The Effect of In-Situ Liner Oxide on Threshold Voltage and Its
Application to Enhance Yield Stability” by Y. H. Wu, C. Y. Wang, W. H.
Hsieh, P. Y. Chang and C. L. Ku; PROMOS TECH.; Taiwan, R.O.C.
5.J
“Elimination of the Aluminum Bubbles from the Metal Interconnect Lines for
the Memory Products” by C. Consalvo, M. Sacchi and A. Privitera; ST
MICROELECTRONICS; Catania, ITALY; A. Sidhwa; ST MICROELECTRONICS; Phoenix,
AZ.
5.K
“Solution to Abnormal Growth of Tungsten Polycide Gate of Logic Embedded
Mask Rom Product” by M. Chang, M. T. Lee; MACRONIX; Taiwan, R.O.C.Coffee
Break 10:40 - 10:55 A.M.
SESSION VI
- 10:55 A.M. - 12:00 P.M.
VLSI MULTILEVEL
INTERCONNECTION
SIMULATION AND MODELING I
Chairman:
Dr. Kaustav Banerjee
UNIVERSITY OF CALIFORNIA
Santa Barbara, California
6.A
“Modeling and Timing with Metal Process Tolerance” by P. Habitz, E.
Foreman; IBM MICROELECTRONICS; Essex Junction, VT.
(Invited
Paper)
6.B “A
Stochastic Algorithm for 3D Maxwell Solution Within Optical On-Chip
Integrated Circuit Interconnects: Materially Heterogeneous Benchmarks”
by Y. L. LeCoz, J. Kalyanasundharam, D. Krishna and R. B. Iverson;
RENSSELAER POLYTECH INST.; Troy, N.Y.
6.C
“Variability - Driven Considerations in the Design of Integrated Circuit
Global Interconnects”by L. He, K. H. Tam, J. Xiong; UNIV. Of
CALIFORNIA; Los Angeles, CA.; A. B. Kahng; UNIV. Of CALIFORNIA; San Diego,
CA.
(Invited
Paper)
6.D “A
Methodology for Predicting Full-Chip Interconnect Thickness Variation on
Production Integrated Circuits at 90 nm and Below” by P. R.
Chidambaram, C. Borst and G. Shinn; TEXAS INSTRUMENTS; Dallas, TX.; A.
Gower, T. Tugbawa, B. Lee and D. White; PRAESAGUS; San Jose, CA.
--- POSTER PAPERS ---
6.E
“Even / Odd Waveform Modeling of Two Conductor Silicon Slow - Wave Loss:
Mitigation by Coupling to Nearby Conductors” by J. Diao, J. Guo, Y. Le
Coz and J. McDonald; RENSSELAER POLYTECH INST.; Troy, N.Y.; W. Wood, R.
Singh; IBM MICROELECTRONICS; Essex Junction, VT.
SESSION
VII - 1:30 - 2:30 P.M.
VLSI MULTILEVEL INTERCONNECTION
POSTER PAPER / EXHIBITION
DEDICATED VIEWING TIME
SESSION
VIII - 2:30 - 5:15 P.M.
VLSI MULTILEVEL INTERCONNECTION
CMP MODELING / PROCESSES
& CONSUMABLES
Chairman:
Dr. Harry Rathore
IBM
MICROELECTRONICS
Hopewell Junction, New York
CMP MODEL &
SIMULATION
8.A
“Characterization and Modeling of the 90 nm Technology Copper CMP Process”
by J. N. Zabasaja, T. Merchant, G. Martin and A. Phillips; FREESCALE
SEMI; Austin, TX.
8.B
“ECP / CMP Characterization and Modeling for 90 nm Node Technology” by
T. Pan, S. Koppikar; APPLIED MATERIALS; Santa Clara, CA.; D. White, K. H.
Chen, T. Tugbawa, B. Lee, S. Shroff, S. Fisher, T. Smith; PRAESAGUS; San
Jose, CA.; D. Fong; VEECO INSTRUMENTS.; Santa Clara, CA.
8.C
“Deficiencies of Copper CMP Models Based on Lookup Tables” by T.
Smith, D. White, R. Moore and V. Mehrotra; PRAESAGUS; San Jose, CA.
--- POSTER
PAPERS ---
8.D
“Fractal Modeling of CMP Pad Texture”by S. M. Song; NORTHERN ILLINOIS
UNIV.; Urbana, IL.; J. C. Sung, Y. L. Pai; KINIK; Taiwan, R.O.C.; M. Y.
Tsai and Y. S. Liao; NAT’L TAIWAN UNIV.; Taiwan, R.O.C.
8.E “A
Friction Model Study on the Defect Control of Direct STI High Selectivity
Slurry CMP” by S. Wang and A. Su; PROMOS TECH.; Taiwan, R.O.C.
CMP PROCESS
DEVELOPMENT II
8.F
“General Principle of Planarization Governing Polish, ECP, ECMP, Etching,
etc. - Low Down Force Planarization Technologies” by M. Tsujimura;
EBARA CORP.; Tokyo, JAPAN.
(Invited
Paper)
8.G “A
Theoretical Study on the Relationship Between Wafer Surface Pressure and
Wafer Backside Loading in CMP” by G. Fu and A. Chandra; IOWA STATE
UNIV.; Ames, IA.
--- POSTER
PAPERS ---
8.H
“Impact of Point-of-Use Filtration on an ILD CMP Process” by B. Johl;
ROHM & HASS; Phoenix, AZ.; M.H. S. Tseng; CUNO; Meriden, CT.
CMP CONSUMABLES
8.I
“Functionally Graded Pad: A Tribological, Thermal and Kinetic
Characterization and Planarity Performance for ILD Polishing” by S.
Misra, E. Hwing, M. Nasrullah, H. Vaidya and P. K. Roy; NEOPAD TECH;
Sunnyvale, CA.; Y. Samporno, Y. Zhuang, M. Sugiyama and A. Philliposian;
UNIVERSITY Of ARIZONA; Tucson, AZ.; M. Deopura, X. Xie and D. Boning;
MASSACHUSETTS INST. Of TECH; Cambridge, MA.
(Invited
Paper)
8.J
“Nanoporous Particle for Polishing of Barrier / Low-k Dielectric Films”
by R. V. Singh; UNIVERSITY OF TEXAS; Austin, TX.; M. Dufourg, K. S. Choi
and D. Singh; SINMAT; Gainesville, FL.
(Invited Paper)
8.K
“Study of the Wear Phenomenon in Copper Abrasive Free CMP” by T.
Haque, S. Balakumar; INST. Of MICROELECTRONICS; SINGAPORE; A. S. Kumar, M.
Rahman; NAT’L UNIVERSITY OF SINGAPORE.
8.L “A
DOE Approach to Predicting Film Selectivities in Barrier Slurries” by
P. M. Van Calcar; FUJIMI; Tualatin, OR.
--- POSTER PAPERS ---
8.M
“Treatment of Copper CMP Waste Streams and Copper Electroplating Rinse
Streams by Direct Ion Exchange” by B. Roberts, J. Jangbarwala; BOC
EDWARDS; Santa Clara, CA.
8.N
“Recent Advances in the Development of Ceria-Based Slurries for Inner
Layer Dielectric CMP” by D. Merricks, B. Santora, B. Her and H.
Goodman; FERRO; Penn Yan, N.Y.
8.O
“Evaluation of TWI STT711 1/4 Inch Groove Pad for WCMP at TSMC Fab 3"
by B. I. Lee, M. S. Chen; T.S.M.C.; Taiwan, R.O.C.; L. Nguyen, G. Wu, S.
Kirtley and T. West; THOMAS WEST; Sunnyvale, CA.
8.P
“Dynamic Pot-Life and Handling Evaluation of Celexis STI Slurry” by B.
Johl and N. Bishop; ROHN & HAAS; Phoenix, AZ.
8.Q
“Characterization of a Novel Rotary Pad Technology for CMP Applications”
by D. Lamb, C. Forrestal, K. Pierce; PRAXAIR; Indianapolis, IN.; J.
Cianciolo, T. Dunn; PRAXAIR; Salem, NH.
8.R
“Ceria-Based Slurries for STI Applications” by B. Santora, D. Merricks,
B. Her and J. Laemlein; FERRO; Penn Yan, N.Y.
8.S
“The Influence of Diluted Direct STI CMP Slurry for STI CMP Process”
by A. Su and M. Chang; PROMOS TECH.; Taiwan, R.O.C.
Saturday,
October 2, 2004
SESSION
IX - 9:00 - 10:00 A.M.
VLSI MULTILEVEL INTERCONNECTION
SIMULATION & MODELING II
Chairman:
Dr. Kaustav Banerjee
UNIVERSITY OF
CALIFORNIA
Santa Barbara, California
9.A
“Multiscale Modeling for Interconnects: Status and Opportunities” T.
S. Cale, M. O. Bloomfield, X. Y. Liu and H. Huang; RENSSELAER POLYTECH
INST.; Troy, N.Y.
(Invited
Paper)
9.B
“Layout Extraction for Global Wires With Metal Process Tolerances” by
P. Habitz and J. Hurst; IBM MICROELECTRONICS; Essex Junction, VT.
(Invited
Paper)
9.C “A
Sum - Over - Paths Impulse - Response Moment Extraction Algorithm for IC -
Interconnet Networks: Verification, Uncoupled RLC Lines” by Y. L.
LeCoz, G. Hariharan, D. Krishna; RENSSELAER POLYTECH INST.; Troy, N.Y.; D.
M. Petranovic; MENTOR GRAPHICS; Wilsonville, OR.
Coffee
Break 10:00 - 10:15 A.M.
SESSION X
- 10:15 - 11:45 A.M.
VLSI MULTILEVEL INTERCONNECTION
DIELECTRIC & NOVEL ISSUES
Chairman:
Dr. Devendra Kumar
ASM CORP.
San Jose, California
DIELECTRIC
SYSTEMS
10.A
“Mechanical Behavior of Low - k Organo-silicates” by W. Volksen, T. P.
Magbitang, G. Dubois; V. Y. Lee, P. J. Brock and R. D. Miller; IBM ALMADEN
LABS; San Jose, CA.; L. Ramirez; UNIVERSITY Of CALIFORNIA; Irvine, CA.;
E. E. Simonyi; IBM WATSON LABS; Yorktown Heights, N.Y.
(Invited
Paper)
--- POSTER PAPERS ---
10.B
“The Characterization of MSSQ - BTMSE Spin - On Organosilicate”by B.
R. Kim, J. W. Kang, K. Y. Lee, J. M. Son and M. J. Ko; LG CHEMICAL;
Daejeon, KOREA.
10.C
“Increasing of Arsenic Diffusion into Silicon From Arsenic-Doped Oxide
Source on Deep Trench Based Capacitor DRAM” by C. Wang, W. Wu and A.
Ku; PROMOS TECH.; Taiwan, R.O.C.
NOVEL SYSTEMS
10.D
“Study of Carbon Nanotubes for Electronic Applications” by J.
H. Ting, J. L. Hsu; NATIONAL NANO DEVICE LAB; Taiwan, R.O.C.; C. C. Chang;
NAT’L CHUNG HSING UNIV.; Taiwan, R.O.C.; M. C. Cheng, F. Y. Huang; NAT’L
CENTRAL UNIV.; Taiwan, R.O.C.
10.E
“Packaging of Low-k / Copper Devices: Implications for On-Chip
Integration” by S. Chungpaiboonpatana, F. G. Shi; UNIV. OF CALIFORNIA;
Irvine, CA.
(Invited Paper)
10.F
“A Comparative Scaling Analysis of Metallic and Carbon Nanotube Contacts
and Vias in Nanometer Scale Interconnect Technologies” by N.
Srivastava, K. Banerjee; UNIV. Of CALIFORNIA; Santa Barbara, CA.
--- POSTER PAPERS ---
10.G
“Evaluation of Aluminum Nitride as the Hinge Material of an Actuator”
by J. H. Ting, J. L. Hsu; NAT’L NANO DEVICE LABS; Taiwan, R.O.C.; J. L.
Liang, F. Y. Huang; NAT’L CENTRAL UNIV.; Taiwan, R.O.C.
2004 VMIC LUNCHEON
Saturday,
October 2; 12:00 - 2:00 P.M.
Luncheon Presentation
(1:30 - 2:00 PM)
“
MATERIALS INTEGRATION OF OPTICAL
INTERCONNECT SOLUTIONS FOR SILICON”
Dr. Mayank Bursara
Co-Founder & Chief Technology Officer
AMBERWAVE
SYSTEMS
Salem, NH
SESSION
XI - 2:00 - 3:30 P.M.
VLSI MULTILEVEL INTERCONNECTION
CMP PROCESSES
Chairman:
Dr. Shoso Shingubara
HIROSHIMA
UNIVERSITY
Hiroshima, Japan
CMP RELIABILITY
11.A
“Defectivity Comparison Between Fumed Silica and Colloidal Silica in
Barrier Polish” by S. Li, P. Feeney, R. Martinez, D. Schroeder, K.
Moeggenborg; CABOT MICROELECTRONICS; Aurora, IL.
--- POSTER PAPERS ---
11.B
“A Solution to Macro Scratching or Orbital CMP Polishers” by A.
Yohannan, R. Nickell, A. Sidhwa, M. Goulding, T. Gandy; ST
MICROELEC-TRONICS; Phoenix, AZ.
11.C
“DRAM Alignment Mark Damaged Improvement in STI CMP” by H. J. Lin, S.
Y. Yang, C. Y. Lee, C. W. Dai, W. C. Liaw, G. Y. Jiang, Y. F. Yang, C. F.
Lee and W. P. Chung; VANGUARD SEMI; Taiwan, R.O.C.
11.D
“Strategy to Study Barrier Chemical Mechanical Polish Defects” by S.
Li, P. Feeney, R. Martinez, D. Schroeder and K. Moeggenborg; CABOT
MICROELECTRONICS; Aurora, IL.
CMP CLEANING
PROCESSES
11.E
“Improved Copper / Low-k CMP Cleaning Methods” by R. W. Donis, P. A.
Burke and L. D. Bauck; LSI LOGIC; Gresham, OR.
CMP CONDITIONERS
11.F
“Nanom CMP Process for Making Future Chips” by J. C. Sung; KINIK;
Taiwan, R.O.C.
11.G
“Amorphous Diamond for Dressing Fixed Abrasive Pad” by J. C. Sung, Y.
L. Pai; KINIK; Taiwan, R.O.C.; P. L. Tso, C. W. Chiu, T. P. Hsu; NAT’L
TSING HUA UNIVERSITY; Taiwan, R.O.C.
--- POSTER PAPERS ---
11.H
“CMP Pad Dressing With Oriented Diamond” by M. Y. Tsai, Y. S. Liao;
NAT’L Taiwan University; Taiwan, R.O.C.; J. C. Sung, Y. L. Pai; KINIK;
Taiwan, R.O.C.
11.I
“Chemical Barrier Coating for CMP Pad Conditioner” by K. Kan, J. C.
Sung, Y. L. Pai, A. Chen and J. Hu; KINIK; Taiwan, R.O.C.
11.J
“Diamond Wear Pattern of CMP Pad Conditioner” by J. C. Sung, Y. L. Pai;
KINIK; Taiwan, R.O.C.; C. T. Yang, P. W. Hung, Y. S. Liao; NAT’L TAIWAN
UNIV.; Taiwan, R.O.C.
CMP EQUIPMENT
---
POSTER PAPERS ---
11.K
“The Influence of Plate Structure in Membrane Embedded Polisher Head”
by G. S. Cho, Y. W. Lee, D. Y. Kim, H. P. Kim, H. S. Jeong, W. S. Yang;
ANAM SEMICONDUCTOR; Kyunggi, KOREA.
11.L
“Chamber Output Matching Procedure for High Density Oxide Etch Tools”
by D. Dopp and J. Conrad; FREESCALE SEMI.; Austin, TX.
SESSION
VII
VLSI MULTILEVEL
INTERCONNECTION
RELIABILITY
ISSUES
--- POSTER PAPERS ---
12.A
“Elimination of the Back Side Pressure Faults for Tungsten Deposition
Process” by J. H. Zhang, G. Magsamen; ST MICROELECTRONICS; Carrollton,
TX.; A. Sidhwa; ST MICROELECTRONICS; Phoenix, AZ.
12.B
“Effect of Poly Silicon Over-Etching Time on Gate Oxide Reliability”
by Y. Zhao; NEC; Shanghai, CHINA; X. Wan; SHANGHAI R & D CTR.; Shanghai,
CHINA.
12.C
“The Liquid Film Curriculum Vitae: Physics & Chemistry of the Phenomena
Occurring During Liquid Film Drying on the Semiconductor Wafer Surface”
by Y. Gotkis and T. H. Lin; LAM RESEARCH; Fremont, CA.
12.D
“The Effect of Chamber Season Condition on Film Surface Charge Status”
by C. Shu; UMC; Taiwan, R.O.C.
12.E
“Premature Failure of the Ceramic Purge Ring Due to Tungsten Build-Up”
by J. H. Zhang, C. Lawrence, M. J. Pelzel, G. Jones, S. L. Toh, G.
Magsamen, A. Sidhwa; ST MICROELECTRONICS; Carrollton, TX.
12.F
“The Mechanism Study of Particle Improvement in Matrix 403 Tool” by J.
H. Chang, D. R. Yang and S. S. Hwu; MACRONIX; Taiwan, R.O.C.
12.G
“Resist, Polymer and Etch Residue Removal From High-k Substrates” by
M. Egbe, D. Geitz and M. Legenza; AIR PRODUCTS & CHEMICALS; Easton, PA.
12.H
“The Effect of Tungsten CVD SiH4 Soak for a Contact Open Issue”
by B.R. Ni, C. J. Liaw, W.P. Chiu, J. Chen, G. Ding; PROMOS TECH.; Taiwan,
R.O.C.
12.I
“Study of Liquid Type Defects Post Tungsten Etch Back Step” by J. H.
Zhang, C. Lawrence, S. L. Toh, G. Magsamen, A. Sidhwa; ST
MICRO-ELECTRONICS; Carrollton, TX.
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NOTICE TO AUTHORS OF POSTER PAPERS
Plan to put ALL posters for ALL SESSIONS up on Friday, October 1, before
9:30 am at the location
designated (Check at Conference Registration Desk). Poster boards will be
provided as indicated in author kits. Be available AT YOUR POSTER to
answer questions during Session VII (from 1:15 - 2:30 pm on Friday).
Plan to remove your poster on Saturday afternoon from 3 - 4
pm, October 2.
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