NINTH INTERNATIONAL
C.M.P. PLANARIZATION
FOR ULSI
MULTILEVEL INTERCONNECTION
CONFERENCE
February
24 - 26, 2004
February 24,
2004
OPENING SESSION - 9:00 A.M.
Welcoming Remarks
Dr. Thomas E.
Wade, Gen. Chmn.
University of South Florida
|
SESSION I -- 9:15 A.M. KEYNOTE ADDRESS “COPPER CMP MANUFACTURING CHALLENGES FOR THE 90 nm NODE AND BEYOND”
Dr. Te Hua Lin Vice President LAM RESEARCH CORPORATION |
Coffee Break 9:45 - 10:00 AM
SESSION II - 10:00 A.M. - 12:15 P.M.
VLSI
MULTILEVEL INTERCONNECTION
COPPER
CMP PROCESSING
|
Chairman: |
Dr. Peter Burke LSI LOGIC Santa Clara, CA |
|
2.A |
“Characteristics of Copper CMP Process for
Ultra- Low Pressure” by S. Hoshino, Y. Uda
and E. Yamamoto; NIKON CORP; Tokyo, JAPAN Invited Paper |
|
2.B |
“Novel Pure Organic Particles for Copper CMP
at Low Down Force” by K. Cheemalapati,
A. Chowdhury, V. Duvvuru
and Y. Li; CLARKSON UNIVERSITY; Potsdam, N.Y.; K. Tang and G. Bian; DYNEA; Mississauga, CANADA. Invited Paper |
|
2.C |
“Copper CMP Process for High Reliable Copper
Damascene Interconnects” by Y. Yamada, N. Konishi,
J. Noguchi and U. Tanaka; HITACHI LTD.; Tokyo, JAPAN. |
|
2.D |
“Electrochemical Approach in Copper CMP” by
E. Ivanov; TOSOH SMD; Grove City; OH.; A. Masliy and A. Zelinsky; INST. Of SOLID STATE CHEMISTRY; Novosibirsk,
RUSSIA. |
|
2.E |
“Stress Free Polishing - A Technique for
Copper Removal in Advanced Technology Nodes” by
J. Pallinti, S. Lakshminaryanan,
W. Barth, L. Kwak, P.
Burke, S. Gu, C. Falk, M. Lu, S.S. Sun, P. Wright,
J. Elmer, L. Duong, S. Reder, R. Donis, W. Catabay; LSI LOGIC;
Gresham, OR.; and D. Wang, B. Hannan, F. Ho, M. Rehayem; ACM RES; San Jose, CA. |
|
2.F |
“300 mm Copper CMP Process Development on a
Single Platen for 65 nm Technology” by R. Barker, M. VanHaneham; RODEL; Phoenix, AZ.; G. Moloney
and H.M. Wang; EBARA TECH; San Jose, CA. |
|
2.G |
“Copper CMP Imposed Design Limitations” by
S. Kordic; PHILIPS SEMICONDUCTOR; Crolles, FRANCE. Invited Paper |
|
|
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POSTER PAPERS --- |
|
2.H |
“Copper CMP Process Development for Copper/
Low-k Materials Using A New Abrasive Free Slurries” by
S. Balakumar, T. Selvaraj,
B. Lin; INST. Of MICROELECTRONICS; Singapore; T. Hague, A. S. Kumar; NAT’L
UNIV. Of SINGAPORE; and S. Honda; MORESCO CORP; Hyogo, JAPAN. |
|
2.I |
“Micelles and Vesicles in Abrasive-Free Copper
CMP Solutions” by J. Zhao, J. Keleher
and Y. Li; CLARKSON UNIV.; Potsdam, N.Y.; W. Wojtczak;
SACHEM; Austin, TX. |
Box Lunches - 12:15 - 1:15 P.M.
Visit Industrial Exhibition/Poster Presentations
SESSION III - 1:15 - 3:15 P.M.
VLSI MULTILEVEL INTERCONNECTION
CMP
PROCESS CHARACTERIZATIONS
|
Chairman: |
Dr. Peter Thieme INFINEON TECHNOLOGY Dresden, Germany |
|
3.A |
“Prediction and Characterization of Indirect
STI CMP on Selected Features Using HDP Oxide” by
P. Beckage, R. Tian, A.
Phillips, C. Thomas, E. Travis and T. Brown; MOTOROLA CORP; Austin, TX. |
|
3.B |
“Dynamical Mechanism of CMP Analyzed by
Frictional Force Measurement” by Y. Homma, H. Kashima,
K. Fukushima; HITACHI LTD; Tokyo, JAPAN; N. Sakuma; ELPIDA MEMORY; and S.
Kondo; SELETE; Tokyo, JAPAN. Invited Paper |
|
3.C |
“Known Effects of Pattern Characteristics on
Copper CMP and Future Plans” by F. M. Doyle; UNIV. Of
CALIFORNIA; Berkeley, CA. Invited Paper |
|
3.D |
“Shear Force Study of Low-k / Copper CMP for
65 nm Generation and Beyond” by L.G. Chen, H.H.Lu, W.C. Chiou, Y.H. Chen,
S.M. Jeng, S.M. Jang, M.S. Liang;
T.S.M.C.; Taiwan, R.O.C. |
|
3.E |
“Experimental and Theoretical Analysis of
Non-Rotating Copper Wafer Polishing” by L. Borucki;
INTELLIGENT PLANAR: Meza, AZ.; A. Jindal, T. Cale, R. Gutman and J. Tichy; RENSSELAER POLYTECH. INST.; Troy, N.Y.; S.H. Ng
and S. Danyluk; GEORGIA INST. Of TECHNOLOGY;
Atlanta, GA. |
|
3.F |
“A Kinematic Study
for Novel Split Pad CMP Technique” by T. Haque,
A. Senthil Kumar, M. Rahman;
NAT’L UNIV. Of
SINGAPORE; S. Balakumar; INST. Of
MICROELECTRONICS; Singapore. |
|
|
---
POSTER PAPERS --- |
|
3.G |
“Process Improvement of a Fixed Abrasive
STI-CMP Process Through Introducing Subpad
Topography” by M. Naujok, D. Souche; INFINEON TECH.; Taiwan, R.O.C.; and H.L. Lu, C.R.
Hsu, T.C. Tsai and G.S. Yang; UNITED MICROELECTRONICS CORP.; Taiwan, R.O.C. |
|
|
---
LATE NEWS PAPERS --- |
|
3.H |
“Advances in Control of Chemical Mechanical
Polishing Head Pressures” J. W. Hill, M. Selser, B.A. Cozad, J.M. Harris, H. Dinh
and A.K. Henning; REDWOOD MICROSYSTEMS; Menlo Park, CA. |
|
3.I |
“Effect of Different Modes of Contact on
Material Removal Rate and Non-Uniformity in Abrasive Free CMP Process” T. Haque, A.S. Kumar and M. Rahman;
NAT’L UNIV. Of SINGAPORE; and S. Balakumar; INST.
Of MICROELECTRONICS; SINGAPORE. |
Coffee Break 3:00 - 3:15 PM
SESSION IV - 3:15 - 5:00 P.M.
VLSI MULTILEVEL INTERCONNECTION
C.M.P. MODELING
& SIMULATION - PART I
|
Chairman: |
Dr. Mansour Moinpour Santa Clara, California |
|
4.A |
“How Mechanical is Chemical Mechanical
Planarization: A Modeling Perspective” by L. Jiang;
INTEL CORP; Santa Clara, CA. Invited Paper |
|
4.B |
“A Computational Study of Slurry Flow in
Grooved CMP Polishing Pads” by G. P. Muldowney; RODEL; Newark, DE; and D. T. Tselepidakis; FLUENT INC; Newark, DE. Invited Paper |
|
4.C |
“Implementation of Model Based Tiling at STI
CMP for 90 nm Technology” by P. Beckage,
R. Tian, A. Phillips, C. Thomas, E. Travis and T.
Brown; MOTOROLA CORP; Austin, TX. |
|
4.D |
“Initial STI Topography Enhancement for a Optimized Post CMP Topography by Integrated Simulation” by
F. Meyer, P. Thieme, M. Hollatz,
S. Parascandola and E. Schiller; INFINEON TECH;
Dresden, GERMANY; and J.W. Bartha; TECH. UNIV. Of
DRESDEN; Dresden, GERMANY. |
|
4.E |
“A Stochastic Model for the Effects of Pad
Surface Topography Evolution on Material Removal Rate Decay in Chemical
Mechanical Polishing” by C. Wang, P. Sherman and A. Chandra; IOWA STATE UNIV.; Ames,
IA. |
|
|
---
POSTER PAPERS --- |
|
4.F |
“Mathematical Model to Simulate the Surface
Topography of CMP Pad by Conditioning on Ebara 300 mm F-REX Polisher” by
L. Nguyen, G. Wu and T. West; THOMAS
WEST; Sunnyvale, CA.; and R. Lin, J. Tung; PROMOS
TECH; Taiwan, R.O.C. |
|
4.G |
“Pad Conditioner Down Force Calibration
Modeling in Mirra CMP Equipment” by
M.F. Koh, A.Repeso, R.
Vega, M. Sivakumar, S. Tampithurai,
M. Rajanogaran, B. Wang, K. C. Tan, Y.S. Koh, T. W. Leong, K.F. Lai,
C.S. Poh; S.S.M.C. (PHILIPS/TSMC/SINGAPORE);
SINGAPORE. |
|
|
---
LATE NEWS PAPERS --- |
|
4.H |
“Accurate Modeling of CMP Induced Process
Corners” by K. J. Chang; NAT’L TSING HUA UNIV.; Taiwan,
R.O.C.; and L. F. Chang; SEQUENCE DESIGN; Santa Clara, CA. |
Wednesday , February 25, 2004
SESSION V -
8:30 - 10:10 A.M.
VLSI MULTILEVEL INTERCONNECTION
CMP
CONSUMABLES - PART I
|
Chairman: |
Dr. Ara Philipossian |
|
5.A |
“A Quantitative Analysis of Multi-Scale
Response of Wet and Dry CMP Pad” by S.D. Gouda, A. Bastawros and A. Chandra; IOWA STATE UNIV.; Ames, IA. |
|
5.B |
“Mechanical Role of Abrasive in Slurry and Its
Impact on Low Down Force Copper CMP” by F. Sun, R. Zhou, M. Kason, R. Martinez; CABOT MICROELECTRONICS; Aurora, IL. |
|
5.C |
“Determining the Effect of Pad Grooving on the
Tribological, Thermal and Removal Rate Attributes
of Copper CMP” by Z.Li, Y. Zhuang and A. Philipossian;
UNIV. Of ARIZONA, Tucson, AZ; and L. Borucki,
INTELLIGENT PLANAR; Mesa, AZ. |
|
5.D |
“Characterization of Oxide CMP Slurries With
Fumed Silica Abrasive Particles Modified by Wet Jet Milling” by
G. Zwicker, H. Jacobsen and E. Stachowiak;
FRAUNHOFER INST.; Itzehoe, GERMANY; and W. Lortz, R. Brandes; DEGUSSA; Hanau, GERMANY. |
|
5.E |
“The Impact of Slurry Backmixing
in Determining Optimal CMP Process Conditions” by G.P. Muldowney,
J.J. Hendron and T.T. Crkvenac;
RODEL; Newark, DE. |
|
|
---
POSTER PAPERS --- |
|
5.F |
“A Model of Pad Conditioner Wear and How to
Extend Pad Life by Compensating for the Wear” by G.
Palmgren; 3 M COMPANY; St. Paul, MN. |
|
5.G |
“TWI 711 Implement in 300 mm Production Line
for Tungsten CMP at Promos” by R. Lin, J. Tung; PROMOS TECH; Taiwan, R.O.C.; G. Wu, L. Nguyen, and
T. West; THOMAS WEST; Sunnyvale, CA.; R. Chan; GRAND TREND; Hsin-Chu, Taiwan, R.O.C. |
|
5.H |
“Minimizing Particles During the CMP Slurry
Dispense Process” by D.J. Albrecht; NT INT’L; Minneapolis, MN. |
|
5.I |
“Handling and Filtration Characterization of a
Collodial Silica Metal CMP Slurry” by R.K.
Singh, G. Conner; MYKROLIS CORP. Billerica, MA; and B.R. Roberts; BOC
EDWARDS; Santa Clara, CA. |
|
5.J |
“Advanced Specification and Tests of CMP
Retaining Rings” by N. Gitis, J.
Xiao; CTR for TRIBOLOGY; Campbell, CA; and A. Kumar, A. Sikder;
UNIV. Of SOUTH FLORIDA; Tampa, FL. |
|
5.K |
“Effects of Diamond Shape and Size on
Polyurethane Pad Conditioning” by M. Bubnick,
S. Qamar, S. McGregor, T. Namola,
T.White; ABRASIVE TECH; Lewis Center, OH. |
|
5.L |
“Copper CMP Barrier Slurries for Ultra Low-k
Applications” by Z. Liu, J. Quanci
and R. Schmidt; RODEL; Neward, DE. |
Coffee Break
- 10:10 A.M. - 10:25 A.M.
SESSION VI - 10:25 - 12:05
P.M.
VLSI MULTILEVEL INTERCONNECTION
CMP
STI & POST CLEANING ISSUES
|
Chairman: |
Dr. Abhijit Chandra |
CMP
SHALLOW TRENCH ISOLATION
|
6.A |
“Characterization and Prediction of Within Die
Thickness Variation at STI CMP on 90 nm Technology” by
P. Beckage, R. Tian, A. Phillips,
C. Thomas, E. Travis, T. Brown; MOTOROLA CORP; Austin, TX. |
|
6.B |
“Development of a Production Worthy Fixed
Abrasive STI CMP for Logic Applications at 90 nm Technology Node and Beyond” by
T.C. Tsai, L. Lu, C.R. Hsu, S.K. Chu, A. Yu, G.S.
Yang, S.F. Tzou and K. Liao;
U.M.C.; Taiwan, R.O.C.; and M. Naujok; INFINEON
TECH; Taiwan, R.O.C. |
|
6.C |
“High Selectivity Colloidal Silica Slurry for
STI CMP” by I. Belov, D. Lamb, C. Forrestal, K. Pierce; PRAXAIR; Indianapolis, IN; G.M.
Hey, L. Puppe,
G. Passing; H.C. STARCH; Leverkusen, GERMANY; and
J. Simpson; H.C. STARCH; Newton, MA. |
|
|
---
POSTER PAPERS --- |
|
6.D |
“Defect Metrology Issues in the Evaluation of
a Low Defectivity Selective Ceria Slurry” by
A.S. Lawing; P. Flanagan, Y. Epshteyn,
T. Becker, N. Bishop, B. Mueller and K. Lindemann;
RODEL; Phoenix, AZ. |
|
6.E |
“New Formulation for Shallow Trench Isolation
CMP” by B. Santora, D. Merricks; FERRO ELECTRONICS; Penn Yan,
N.Y. |
|
|
CMP
POST CLEANING PROCESSES |
|
6.F |
“A New Method for Determining the Lubrication
Mechanism of Post ILD CMP Brush Scrubbing Using Spectral Analysis of the
Frictional Force Signals” by A. Philipossian,
L. Mustapha, D. King and J. Weaver; UNIV. Of ARIZONA; Tucson, AZ. Invited Paper |
|
6.G |
“Post CMP Cleaning: Challenges and Direction” by
J.G. Park, HANYANG UNIV.; Ansas, KOREA; and A. Busnaina; NORTHEASTERN UNIV.; Boston, MA. Invited Paper |
|
|
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POSTER PAPERS --- |
|
6.H |
“Post Polish Slurry Residue Prevention in an Unconventional
Planarization” by V. Dunton, B. Herner, S. Hu, J. Gu, D. Kidwell, M. Konevecki,
K. Park, C. Petti, M. Mahajani,
S. Radigan, U. Raghuram,
V. Eckert and J. Vienna; MATRIX SEMICONDUCTOR; Santa Clara, CA. |
|
6.I |
“Optimizing the Cleaning Processes After
Copper CMP” by Y. Epshteyn, T. Buley and T. Tran; RODEL; Phoenix, AZ.; and C. Tran;
ATMI; Bethlehem, PA. |
|
6.J |
“Analysis of the Removal of Particles During
Post CMP Cleaning” by T. Zhang, H. Liang,
J.Lee; UNIV. Of ALASKA; Fairbanks, ALASKA; K. Bahten; RIPPEY; El Dorado Hills, CA.; and E. Estragnat, J.M. Martin; ECOLE CENTRAL de LYON; FRANCE. |
Wednesday Lunch on Your Own
Not Provided by Conference
SESSION VII - 1:00 P.M. -
2:30 P.M.
VLSI MULTILEVEL INTERCONNECTION
DEDICATED
TIME FOR CMP
POSTER PAPERS, EXHIBIT VIEWING
SESSION VIII - 2:30 P.M. -
5:00 P.M.
VLSI MULTILEVEL INTERCONNECTION
C.M.P.
PROCESS CHARACTERIZATION &
NOVEL
PROCESSING
|
Chairman: |
Dr. David Hansen |
CMP
PROCESS CHARACTERIZATION
|
8.A |
“CMP for a Low Capacitance Self Aligned
Contact Integration Scheme” by P. Thieme,
H. Drummer, W. Graf and L. Heineck; INFINEON TECH;
Dresden, GERMANY. Invited Paper |
|
8.B |
“Relationship Between Patterned Wafer
Topography Evolution and STI CMP Motor Current Endpoint Signals” by
D. Boning and X. Xie; MASSACHUSETTS INST. Of TECH;
Cambridge, MA.; J. Sorooshian
and A. Philipossian; UNIV. Of ARIZONA; Tucson, AZ.;
D.Stein and D.
Hetherington; SANDIA NAT’L LABS; Albuquerque, NM. Invited Paper |
|
8.C |
“Impact of Temperature on Polishing Pad in a
Tungsten Process” by C. Kok, R. Soh, O.C. Hui and N.T. Leong; S.S.M.C.; SINGAPORE; and G. Koh,
C. Kuo and B. Foster; RODEL; Newark, DE. |
|
8.D |
“Impact of Pattern Density on the Effective
Pressure During STI CMP” by J. Sorooshian,
A. Philipossian; UNIV. Of ARIZONA; Tucson, AZ; L. Borucki; INTELLIGENT PLANAR; Mesa, AZ.; R. Timon, D. Stein, D. Hetherington; SANDIA NAT’L LABS;
Albuquerque, NM: and D. Boning; MASSACHUSETTS INST. Of TECH; Cambridge, MA. |
|
|
--
POSTER PAPERS --- |
|
8.E |
“Optimization of Distribution Loop Filtration
and Its Impact on Copper CMP Process” by A. Pamatat,
B. Bottema, K. Cline; MOTOROLA; Austin, TX.; and H.S.
Tseng; CUNO INC.; Meriden, CT. |
|
8.F |
“Impact of Electroplated Copper Thickness on
Copper CMP and Copper / Low-k BEOL Integration” by
C.H. Seah, G. Z. You, C.Y. Li and R. Kumar; INST.
Of MICROELECTRONICS; SINGAPORE. |
|
8.G |
“The Effect of Slurry Feeding Point Change on
Polishing Uniformity” by J. Tung and R.
Lin; PROMOS TECH.; Taiwan, R.O.C. |
|
|
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NOVEL PROCESSES --- |
|
8.H |
“The Use of Modified Processes to Reduce Feature
Density Effects Observed During Contact Planarization Processes” by
M. Daffron, W.S. Shih and R. Rich; BREWER SCIENCE;
Rolla, MO. |
|
8.I |
“Rapid Low-Cost Development of a Planarized 3 -Level Interconnect Module” by R.
L. Rhoades; POLISHING SOLN; Tempe, AZ.; and R. Danzl;
MEDTRONIC; Tempe, AZ. Invited Paper |
|
|
---
LATE NEWS PAPER --- |
|
8.J |
“The Application of CMP Processing for Single
MEMS Wafers While Maintaining High Volume Results for WTWNU and WIWNU” by
J.J. McAneny and J.H. Welty;
LOGITECH; Old Kilpatrick, SCOTLAND. |
Thursday, February 26, 2004
SESSION IX - 9:00 - 10:00 A.M.
VLSI MULTILEVEL INTERCONNECTION
CMP
MODEL & SIMULATION - Part II
|
Chairman: |
Dr. David Stein SANDIA NAT'L LABS Albuquerque, New Mexico |
|
9.A |
“Multiscale Modeling
of Chemical Mechanical Planarization” by T.S. Cale
and J. A. Tichy; RENSSELAER POLYTECH. INST.; Troy,
N.Y.; L.J. Borucki; INTELLIGENT PLANAR; Mesa, AZ Invited Paper |
|
9.B |
“CMP Process Model Considering Frictional Heat
Generation by BEM” by T. Yoshida; Y.N.T.; Yamaguchi, JAPAN. Invited Paper |
|
9.C |
“A CMP Model for Thermal Oxide ILD” by
E. Paul; STOCKTON COLLEGE; Pomona, N.J.; and A. Philipossian;
UNIV. Of ARIZONA; Tucson, AZ Invited Paper |
Coffee Break 10:00 A.M. -
10:15 A.M.
INVITED SESSION
SESSION X - 10:15 A.M. -
11:15 A.M.
VLSI
MULTILEVEL INTERCONNECTION
C.M.P.
SLURRY INNOVATIONS
|
Chairman: |
Dr. Yuzhuo
Li CLARKSON UNIVERSITY |
|
10.A |
“Copper CMP for 3D Chip With Through Wafer
Vertical Interconnects” by P. Lefevre, K.
Ina, K. Sakai, K. Tamai, S. Rader and P. VanCalcar; FUJIMI; Tualatin, OR. Invited Paper |
|
10.B |
“Integration Issues and Challenges for Copper
Low-k Processes” by A. Zutshi;
DUPONT/EKC TECH.; Hayward, CA. Invited Paper |
|
10.C |
“Wafer Characterization and Spent Slurry
Evaluation With a Novel Pad Conditioner” by C. Burkhard, J. Zhao, P. Wu and Y. Li; CLARKSON UNIV.;
Potsdam, N.Y. |
|
10.D |
“Effect of Ammonium Polycarboxylate
(APC) in Ceria Based Slurry During CMP” by J.D. Lee, J.K. Choi, C. Hong, W.S. Han, J.T. Moon and B.I. Ryu; SAMSUNG; Gyeonggi, KOREA. |
|
10.E |
“Molecular Structure of Chelating Agent and
Its Effect on CMP Performance” by G. Bian
and Y. Li; CLARKSON UNIV.; Potsdam, N.Y.; and B. Shi, A. Fairchild and H. Liang; UNIV. Of ALASKA;
Fairbanks, ALASKA. |
|
|
---
POSTER PAPERS --- |
|
10.F |
“Low Defectivity,
Ceria Based STI Slurry” by B. Mueller, P. Flanagan, N. Bishop; RODEL;
Newark, DE; S. Lawing, Y. Epshteyn,
T. Becker; RODEL; Phoenix, AZ; and D. Coy and P. Murray; NANOPHASE TECH.;
Romeoville, IL. |
|
10.G |
“Conditioning Copper Residue Remover (CCRR)
for Copper Chemical Mechanical Planarization - Chemical Development With
Thomas West Hard Porous Pad” by L. Nguyen, P. Galvez,
G. Wu and T. West; THOMAS WEST; Sunnyvale, CA. |
|
10.H |
“The Implementation of Tungsten CMP Slurry Dilution
With D.I.W in ratio 1:1 Based Acidic Silica Oxidizer” by
B.Y.M. Sub, S.F. Lee, J.T.L. Hook, F.L.H. Ming, A. Minhar,
F.T. Min and N.G.Y. Khoi; FIRST SILICON; Sarawak,
MALAYSIA. |
|
10.I |
“Effect of Particle Size on Removal Rates in
CMP” by D. Tamboli, M. Waddell,
S. Hymes and G. Banerjee;
AIR PRODUCTS; Dublin, OH. |
|
10.J |
“Slurry Flow Rate Calibration Modeling in Mirra CMP Equipment” by M.F. Koh, A. Repeso, R. Vega, M. Sivakumar, S. Tampithurai, M. Rajanogaran, B. Wang, K.C. Tan, Y.S. Koh,
T.W. Leong, K.F. Lai and C.S. Poh;
SYS on SILICON MFG. CO.; SINGAPORE. |
|
10.K |
“Advanced Filtration of Fumed Silica Slurries” by
S.H. Mohseni, L.L. Gramm,
G. Morr and D. Mahulikar;
PLANAR SOLUTIONS; Queen Creek, AZ. |
CMP-MIC LUNCHEON - 12:15 - 2:00
P.M.
“ WHAT THE INTERNATIONAL
TECHNOLOGY ROADMAP FOR
SEMICONDUCTORS (I.T.R.S.)
DOES & DOES NOT SAY ABOUT
CHEMICAL MECHANICAL PLANARIZATION”
Dr. Paul Feeney
CABOT MICROELECTRONICS CORP.
Aurora, Illinois
SESSION XI - 2:00 P.M. - 4:00
P.M.
VLSI MULTILEVEL INTERCONNECTION
C.M.P.
INSTRUMENTATION & HARDWARE,
RELIABILITY
& DIELECTRIC PROCESSES
|
Chairman: |
Dr. Norm V. Gitis |
CMP
INSTRUMENTATION & HARDWARE
|
11.A |
“A Structural Metrology Approach to Measuring
and Monitoring Post-CMP Processes and Evaluation of Related Total Measurement
Uncertainty and Total Process Precision” by W. Lu, C.N.
Archie; IBM MICROELECTRONICS; East Fishkill, N.Y.; P. Chitturi,
H.H. Kang, S. Stone; FEI CO; Hillsboro, OR. |
|
11.B |
“Control of Local Area Removal by Different
Carrier Concepts” by G. Morsch; PETER
WOLTERS; Rendsburg, GERMANY. Invited Paper |
|
11.C |
“A Novel Metrology Tool for ECD and Copper CMP
Surface Profiling” by J. Poris, E. Apak and C. Rampoldi;
NANOMETRICS; Milpitas, CA. |
|
|
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POSTER PAPERS --- |
|
11.D |
“Active Piezo-Controlled
Carrier for Chemical Mechanical Polish Systems” by
C.T. Weber, M.Markworth and J. Weiser;
IGAM ENGR. CO; Barleben, GERMANY. |
|
11.E |
“Opti-Probe RT/CD
Technology for Tungsten Erosion Applications in CMP Processes” by
L. Hsu, A. Su, C.L. Chen, H.H. Chou; PROMOS TECH.; Taiwan, R.O.C.; and Z. Jiang, S. Lee, Y. Wen, E. Wang
and K. Wang; THERMA WAVE; Fremont, CA. |
|
11.F |
“A Linear Removal Model for Chemical
Mechanical Planarization Using a Multizone Membrane
Carrier (M-Carrier)” by T.S. Hubsch, M. Langenkamp, M. Lauter, H. Moller and G. Morsch; PETER
WOLTERS; Rendsburg, GERMANY. |
|
|
CMP
RELIABILITY ISSUES |
|
11.G |
“Effect of Copper Seed Thickness and Agglomer-ation on CMP Peeling and Electric Properties” by
S. Balakumar, T. Selvaraj,
L.B. Fu, C.Y. Li and T. Hara; INST. Of MICROELECTRONICS; SINGAPORE. |
|
11.H |
“Study of the Improvement in the TDDB Reliability
for Copper / Low-k Integration” by N. Konishi,
Y. Yamada, J. Noguchi and U. Tanaka; HITACHI LTD; Tokyo, JAPAN. |
|
|
---
POSTER PAPERS --- |
|
11.I |
“Influence of the Edge Photo Resist Removal on
Post CMP Oxide Thickness” by F. Weber; INFINEON
TECH.; Regensburg, GERMANY. |
|
|
CMP
DIELECTRIC PROCESSES |
|
11.J |
“Advanced CMP Process for Coral Low-k
Integration” by D.A. Hansen, NOVELLUS; San Jose, CA. Invited Paper |
|
|
---
POSTER PAPERS --- |
|
11.K |
“Oxide Chemical Mechanical Polishing With
Advance Process Control” by K. Lim, T.H.Lim;
APPLIED MATERIALS; and M. Teo, A. Jabar and C.W. Lee; ST MICROELECTRONICS; REP. Of
SINGAPORE. |
|
11.L |
“Process Optimization of Oxide CMP for Scratch
Level Improvement” by T. Weinberger and L. Yerushalmi;
TOWER SEMICONDUCTOR; Ha’ Emek, ISRAEL. |
NOTICE
TO AUTHORS
OF
POSTER PAPERS
Plan to put ALL posters for ALL SESSIONS up on
Tuesday, February 24, before 9:30 am at the location designated (Check
at Conference Registration Desk). Poster boards will be provided as indicated
in author kits. Be available AT YOUR
POSTER to answer questions during Session VII (from 1 - 2:30 pm on Wednesday,
Feb. 25). Plan to remove your poster
on Thursday afternoon from 3 - 4 pm. All posters are to be down for room
clean-up by 4 pm on Thursday, February 26.