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Monday, September 22, 2003 This year’s state-of-the-art SEMINAR will address those issues associated with current fundamental developments in advancing VLSI/ULSI multilevel interconnection towards greater functionality, density and speed. It will include a review and discussion of those primary topical areas which impact today's multilevel interconnection event as well as project future direction for this critical industry. A distinguished set of lecturers will participate in this SEMINAR, which is a MUST for all engineers, managers and technicians working on VLSI/ULSI multilevel interconnection. The registration fee includes coffee breaks, luncheon and a visuals booklet. THIS COURSE HAS LIMITED ENROLLMENT. YOU ARE ENCOURAGED TO ADVANCE REGISTER EARLY. TOPICAL COVERAGE I. INTRODUCTORY REMARKS ( 9:00 A.M.) II. DIELECTRICS: (9:15 A.M.) Coffee Break (10:00 A.M.) III. COPPER INTERCONNECTS: IV. RELIABILITY: (11:00 A.M.) Seminar Luncheon (12:00 P.M.) V. THERMAL EFFECTS: (1:45 P.M.) VI. CMP: (2:30 P.M.) Coffee Break (3:15 P.M.) VII. 3-D INTEGRATED CKTS: (3:30 P.M.) VIII. METROLOGY: (4:15 P.M.) IX. CLOSING REMARKS ( 5:00 P.M.)
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