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CONFERENCE September 23 - 25, 2003 ADVANCE PROGRAM
Tuesday,
September 23, 2003
Welcoming
Remarks by the General Chairman
SESSION I
--- 9:15 A.M.
MICRO/NANOELECTRONICS - Coffee Break 9:45 - 10:00 A.M.
Chairman: Dr. Willi Volksen
2.D “Measurement of Elastic Moduli of Low-k Dielectric Films Using Laser-Induced Surface Acoustic Waves” by M. Gostein, A. Mazurenko, A. Maznev, J. Tower; PHILIPS ADV. METROLOGY SYS; Natick, MA.; and S.H. Brongersma; I.M.E.C.; Leuven, BELGIUM. 2.E “Process Integration of NANOGLASS E Porous Ultra Low-k Material (k = 2.2) With Copper Metallization” by X.T.Chen, Y.W. Chen, B. R. Murthy, S. Balakumar, C. Y. Li, C .K. Chang, M. Mukherjee-Roy, Y.J. Su; INST. Of MICRO-ELECTRONICS; SINGAPORE; and A. Naman; HONEYWELL; Sunnyvale, CA. 2.F “The Process Integration Study on Copper/Porous SiOxNy” by L.S. Ke, J.F. Liu and F.S. Huang; NAT’L TSING HUA UNIV.; Taiwan, R.O.C.
--- POSTER PAPERS--- 2.G “High-k Dielectrics for Frequency Agile Appli-cations” by C.J. Wang, C.Y. Hung, D.G. Chou L.M. Chen; UNION CHEMICAL LABS; Taiwan, R.O.C. 2.H “Single Wafer Wet Cleans of Porous SiLK” by L. Archer; SEZ AMERICA; Phoenix, AZ.; and M. Simmonds; DOW CHEMICAL; Leuven, BELGIUM; and K. Itchhaporia; DOW CHEMICAL; Fremont, CA. 2.I “Mechanical and Electrical Strength Improvement for Low Dielectric Constant Materials” by Y.L. Huang, S.H. Lin, Z.C. Wu, T.J. Chou, W. Chang, S.M. Jang, M.S. Liang; T.S.M.C.; Taiwan, R.O.C. 2.J “Integration of Ultra Low-k Aurora With Copper Damascene Metallization” by C.F. Tsang, S. Balakumar, C.Y. Li, V. Bliznetsov, A. Krishna-moorthy, Y.J. Su; INST. Of MICROELECTRONICS; SINGAPORE; and N. Matsuki; ASM JAPAN; Tokyo, JAPAN. 2.K “FCSG: A Proposal of a Novel CVD Low-k Dielectric” by H. Xiao; AUSTIN C.C.; Austin, TX. 2.L “Dielectric Reliability Assessment of Copper / Low-k Damascene Interconnects” by A. Krishnamoorthy, T.C. Fo, B. Subramanian, V. Bliznetsov and J. Su; INST. Of MICROELECTRONICS; SINGAPORE; and Y. Tominori; ASM JAPAN; Tokyo, JAPAN.
Box Lunches -
12:00 -
1:30 P.M.
SESSION III -
1:30 - 3:30 P.M.
Chairman: Dr. Katia Devriendt CMP CONDUCTOR PROCESSES
3.A
“Robust Copper Abrasive-Free Polishing For 90 Nanometer Node Process”
by Y. Yamada and N. Konishi; HITACHI LTD;
Tokyo,
JAPAN. 3.B “Optimizing Tungsten CMP In The Age of Copper” by R. Donis, J. Kalpathy-Cramer, J. Pallinti and D. Vijay; LSI LOGIC; Gresham, OR. 3.C “Copper CMP Planarity and With-In-Die Rs Improvements on 90 nm Copper / Low-k Interconnects” by W. Hong, C.W. Chung, W.C. Chiou, Y.H. Chen, S.M. Jang and M.S. Liang; T.S.M.C.; Taiwan, R.O.C.
3.D
“Copper CMP Process With a Two-Chemistry System on a Linear Planarization
Technology Polisher” by R. Small, B. Scott and P. Chelle; DUPONT EKC
TECH; Hayward, CA.; and Y. Fang, R. Charatan, C. Sainio and P. Cheng; LAM
RESEARCH; Fremont, CA.
--- POSTER PAPERS --- 3.E “Process and Yield Improvement by Changing Consumables in Tungsten CMP” by R. Lin and J. Tung; PROMOS TECH; Taiwan, R.O.C.; and L. Nguyen, T. West, S. Kirtley and G. Wu; THOMAS WEST; Sunnyvale, CA. 3.F “Copper CMP Process Development for Copper / Ultra Low-k Materials” by S. Balakumar, T. Selvaraj, B. Lin, Y.W. Chen, M. Mukherjee-Roy, R. Kumar; INST. Of MICROELECTRONICS; SINGAPORE; and J. Chee; CABOT MICRO; SINGAPORE.
CMP RELIABILITY
3.G
“CMP Process for Copper / Low-k Interlayer Multilevel Interconnections”
by S.Balakumar; INST. Of MICROELECTRONICS; SINGAPORE; and T. Hara;
HOSEI UNIV.; Tokyo, JAPAN. 3.H “Ability of Preventing Delamination for Low-k Film With Air Float Concept CMP Head in Copper CMP” by A. Ueno, T. Yokoyama, A.Yamane and A. Isobe; ACCRETECH; Tokyo, JAPAN.
--- POSTER PAPERS --- 3.I “A Study on CMP Scratches” by G. Fu; IOWA STATE UNIV.; Ames, IA. 3.J “Investigation of Effective Methods to Predict and Control Microscratches in Novel STI CMP Applications” by S.N. Peng, Y.C. Chen, C. Son, S.C. Wang, V. Huang, W.K. Yeh and B.T. Lin; T.S.M.C.; Taiwan, R.O.C.; P. Lee and S. Liu; CABOT MICRO; Taiwan, R.O.C.; R. Huang and G. Tu; MARKETECH INTL; Taiwan, R.O.C. 3.K “A Study Toward Edge Exclusion 1 mm: Substrate Shape and Polishing Profile Correlation” by T. Fukui, K. Tanaka, M. Numoto, A. Yamane and A. Isobe; ACCRETECH; Tokyo, JAPAN.
Coffee Break 3:30 - 3:40 P.M.
SESSION IV -
3:40 - 5:00 P.M. PROCESS CHARACTERIZATION
Chairman: Dr.
Maximilian Biberger
4.A
“Electroless Deposition as Enabling Technology for Semiconductor
Processing” by I. C. Ivanov; BLUE29; Sunnyvale, CA.
4.B
“Development of a BEOL Post Etch Cleaning Process for Copper / Low-k
Integration Using SEZ Single Wafer Processor” by L. Broussous, P.
Besson, O. Hinsinger; STM MICRO; Crolles, FRANCE; T. Billon; CEA-LETI;
Gernoble, FRANCE; S.A. Henry and M. Frank; SEZ AG; Villach, AUSTRIA.
--- POSTER PAPERS --- 4.E “Golden Parameter Ratio Application in the WEB Recipe Development” by J. H. Zhang and G. Magsamen; ST MICROELECTRONICS; Carrollton, TX; and A. Sidhwa; ST MICROELECTRONICS; Phoenix. AZ. 4.F “Patterning of Copper Using Microcontact Printing of SAMs” by N.H. Kim, E.G. Chang; CHUNG-ANG UNIV.; Seoul, KOREA; J.H. Lim; GROWELL TELECOM; Seoul, KOREA; Y.J. Seo; DAEBUL UNIV.; Chonnam, KOREA; and S.Y. Kim; ANAM SEMICONDUCTOR; Kyunggi-do, KOREA. 4.G “A State-of-the-Art Hardmask Enhanced Copper / Low-k Dual Damascene Integration for 90 nm and 65 nm Devices” by W.J. Park, I.G. Kim, J.H. Chung, S.R. Hah, S.W. Nam, I.S. Jo and K.M. Park; SAMSUNG ELECTRONICS; Kyunggi-do, KOREA. 4.H “The Study on Mechanism of Contact Etching Stop With C4F8 / CF4 Chemistry in Lam Exelan Tool” by T. Su and T.H. Chang; MACRONIX INT’L; Taiwan, R.O.C. 4.I “Evaluation of a Zirconium Oxide Coated Belljar and Quartz Insulator Used For a Soft Sputter Etch Process” by A. Sidhwa, M. Goulding, T. Gandy and C. Spinner; ST MICROELECTRONICS; Phoenix, AZ; and D. Laube, I. Davis; BOC EDWARDS; Phoenix, AZ. 4.J “Impact Reliability of Solder Joints” by M. Date and K.N. Tu; UCLA; Los Angeles, CA.; T. Shoji, M. Fujiyoshi and K. Sato; HITACHI METALS; Yasugi, JAPAN. 4.K “Characterization of a Soft Sputter Etch Process for Non-Salicide Contact Technology” by A.Sidhwa, M. Kalaga, E. Morgan, K. Bapatla, M. Goulding, R. Sampson and T. Gandy; ST MICROELECTRONICS; Phoenix, AZ. 4.L “Development of SiCr Thin Film Resistor for SiGe RF-BiCMOS Technology” by H. Sun, K.M. Lau and P. McDonald; PHILIPS SEMICONDUCTOR; Hopewell Junction, N.Y. 4.M “Elimination of Aluminum Cube, Abnormal Aluminum Grains and Wafer Breakage by Modifying the High Temperature Clamp Ring Used in Aluminum PVD Deposition Chambers” by A. Sidhwa, M. Goulding, T. Gandy and C. Spinner; ST MICROELECTRONICS; Phoenix, AZ.
4.N
“Impact of Substrate Thickness on CMOS LC-VCO” by Y.Z. Xiong and A.B.
Ajjikuttira; INST. Of MICROELECTRONICS; SINGAPORE. Wednesday, September 24, 2003
SESSION V -
9:00 - 10:20 A.M.
Chairman:
Dr. Loren W. Linholm
5.A
“3D Hyper-Integration Using Dielectric Glue Wafer Bonding of 200 mm
Wafers” by J.Q. Lu, Y. Kwon, J.J. McMahon, A. Jindal, T.S. Cale; R.J.
Gutmann; RENSSELAER POLYTECH. INST; Troy, N.Y.; B. Altemus, D. Cheng, E.
Eisenbraun; UNIV of ALBANY; Albany, N.Y.
5.C
“Wafer Process of Three Dimensional LSI Chip Stacking Technology With
Copper Interconnection Through Silicon Wafer” by M. Hoshino, Y.
Taguchi, K. Marusaki, M. Ueno, Y. Nemoto and K. Takahashi; A.S.E.T.;
Ibaraki, JAPAN. 5.D “Interconnection Impact Study for a 3D Chip-Stack Computer Core” by J.F. McDonald, R.P. Kraft, P. Belemjian, O. Erdogan and J. Mayega; RENSSELAER POLYTECH. INST.; Troy, N.Y.
Coffee Break 10:20 - 10:35 A.M.
(Invited Session)
Chairman: Dr. David Stein
6.A
“More Than Density: Pattern Dependencies in the Copper Era” by T.
Smith; PRAESAGUS;
San Jose,
CA.
6.B
“How to Clean Very Dirty Wafers After CMP” by M. Ravkin; LAM RESEARCH;
Fremont,
CA.
6.C
“Chemical and Electrochemical Characterization of Peroxide-Induced
Passivation of Copper in Aqueous Glycine Solutions” by F. Doyle and L.
Wang; UNIV. Of CALIFORNIA; Berkeley, CA.
6.D
“Modeling Removal Rates in Chemical-Mechanical Planarization” E. Paul;
STOCKTON COLLEGE; Pomona, N.J.
6.E
“Copper Chemical - Mechanical Planarization Challenges” by M. Oliver;
RODEL;
Newark,
DE.
SESSION VII --- POSTER PAPERS --- 7.A “A Novel Fabrication of Copper Interconnection by Displacing the Pre-Patterned Ti Film for ULSI” by C.H. Yang, W.L. Yang, D.G. Liu, T.J. Yang and G.S. Chen; FENG CHIA UNIV.; Taiwan, R.O.C. 7.B “Studies of Various Effects on the Tungsten Deposition Film That Are Used for High Aspect Ratio Plug Fill Process” by J. H. Zhang, G. Magsamen; ST MICRO-ELECTRONICS; Carrollton, TX; and A. Sidhwa; ST MICROELECTRONICS; Phoenix, AZ. 7.C “Resistivity of 75 nm Node Copper Interconnection Layer - Reduction of Resistivity in Electroplated Copper Line” by T. Hara and Y. Shimura; HOSEI UNIV; Tokyo, JAPAN. 7.D “Development and Characterization of a Top Capacitor Plate for Radio Frequency Applications Using a Metal-Insulator-Metal Process Embedded in a SiGe BiCMOS Technology” by A. Sidhwa, E. Vandenbossche, X. Breurec, M. Kalaga, M. Goulding, O. Xaiyaratt, R. Sampson and T. Gandy; ST MICRO-ELECTRONICS; Phoenix, AZ. 7.E “Aging Effects of PEG and SPS on Filling Capability of Copper Electrochemical Deposition” by T.C. Li, C. Chen; CHIAO TUNG UNIV; Taiwan, R.O.C.; J.M Shieh, B.T. Dai; N.D.L.; Taiwan; S.C. Chang, Y.L. Wang; T.S.M.C.; Taiwan. R.O.C.; J. Ting; MERCK-KANTO CHEMICAL; Taiwan, R.O.C. 7.F “The Influence of Nitrogen on Tungsten Film Stack Deposited at 425ºC and 475ºC Temperature for Interconnect Applications”by A. Sidhwa, M. Gonsalves, X. Breurec, M. Goulding and T. Gandy; ST MICRO-ELECTRONICS; Phoenix, AZ
Wednesday Lunch on Your Own
SESSION VIII - 1:15 - 2:15 P.M.
SESSION IX -
2:15 - 5:15 P.M.
Chairman: Dr.
Anantha Sethuraman
CMP MODEL & SIMULATION
9.A
“Model Based Wafer-to-Wafer Control for Copper CMP” by F. Ko, J.S.
Lin, P.H. Chen, S. Wu, H. Lo, M.S. Zhou and M.S. Liang; T.S.M.C.; Taiwan,
R.O.C.; and J. Zou, T. Mullins, J. Moyne and K. Edwards; BROOKS
AUTOMATION; Andover, MI. 9.B “The Oxide CMP Auto Feed Back System Optimization by Multivariables Linear Regression Model” by Y. Huang, S. Wang, A. Su and J.C.S. Chu; PROMOS TECH; Taiwan, R.O.C.
9.C
“A Comprehensive Material Removal Model for Chemical Mechanical
Planarization” by W. Che, Y. Guo, A. Chandra and A. Bastawros; IOWA
STATE UNIV.; Ames, IA.
CMP CONSUMABLES 9.D “Evaluation of Copper CMP Slurries: Study on Relationship Between CMP Performance and Slurry Formulations” by D. Merrricks, S. Mao and B. Her; FERRO CORP; Penn Yan, N.Y.; and K. Itchhaporia, M. Simmonds; DOW CHEMICAL; Midland, MI.
9.E
“CMP Consumables: New Directions for Per-formance and Cost” by J.
Mendonca, D. Douglass, S. Li, S. Huey, G. Bonne, R. Jackson, W. Hsu, G.
Sin, Y. Ma and M. Wohlert; APPLIED MATERIALS; Santa Clara, CA. 9.F “Chemically Enhanced Copper Polishing With Abrasive-Free “Micelle Slurry”- Part II” by K. Okita, H. Ishimura, S. Funakoshi and H. Tkahashi; ASAHI KASEI; Kanagawa, JAPAN; and T.K. Doy; SAITAMA UNIV.; Saitama, JAPAN.
--- POSTER PAPERS --- 9.G “Effects of Oxidizer Additive on the Performance of Copper Chemical Mechanical Polishing Using Tungsten Slurry” by W.S. Lee; G.W. Choi, CHOSUN UNIV.; Gwang-Ju, SOUTH KOREA; Y.J. Seo; DAEBUL UNIV; Chonnam, KOREA. 9.H “The Implementation of Tungsten CMP Slurry Dilution With D.I.W. in Ratio 1:1 Based Acidic Silica Oxidizer” by B.Y.M. Sub, S.F. Lee, J.T.L. Hook, F.L.H. Ming, A. Minhar, F.T. Min and N.G.Y. Khoi; FIRST SILICON; Sarawak, MALAYSIA. 9.I “Studies on Copper Damascene CMP Slurries: Semiconductor Dissolution in Chemical Mechanical Planarization Process” by S. Mao, D. Merricks and B. Her; FERRO CORP; Penn Yan, N.Y. 9.J “Oxide CMP Characteristics of Mixed Abrasive Slurry by Adding of Annealed Alumina Powder” by Y.J. Seo, C.J. Park; DAEBUL UNIV; Chonnam, KOREA; W. Lee; CHOSUN UNIV; Gwang, KOREA.9.K “CMP Pad Conditioners: The World Trend of Using Diamond Grid” by J. Sung; KINIK; Taiwan, R.O.C. 9.L “Aging Effects of Silica Slurry and Oxide CMP Characteristics” by W.S. Lee, P.J. Ko; CHOSUN UNIV.; Gwang, KOREA; Y.J. Seo; DAEBUL UNIV; Chonnam, KOREA. 9.M “Copper CMP Property by Addition of Corrosion Inhibitor and Complexing Agent” by J.D. Jeong, Y.S. Kim, Y.W. Kim, D.Y. Kim, S.Y. Kim, J.S. Choi and K.W. Lee; ANAM SEMI; Kyunggi-do, KOREA.
CMP PROCESS
9.N
“Chemical Mechanical Planarization for Re-generating Defect-Free Bare
Silicon” by J.P. Williams and K. Wooldridge; INTEL CORP; Albuquerque,
NM.
--- POSTER PAPERS --- 9.O “Dynamic Pot-Life and Handling Evaluation of Rodel RLS3126 Reactive Liquid Copper Clearing Chemistry” by B. Johl, A. Manzonie; RODEL; Phoenix, AZ.
CMP DIELECTRICS
9.P
“Evaluation of Direct Copper CMP on Porous SiLK Low-k Materials” by
H.M. Wang, A. Reyes, G. Moloney, N. Kimura, M. Simmonds; EBARA TECH.; San
Jose, CA.; and K. Itchhaporia, G. Bauer; DOW CHEMICAL; Midland, MI. 9.Q “Copper Damascene Integration for an Advanced Carbon Doped Oxide Low-k Film Using the Momentum 200 mm CMP Tool” by D.A. Hansen, M. Grief, F. O’Moore, J. Schlueter; NOVELLUS SYS; Chandler, AZ.; D. Vitkavage, G. Ray; NOVELLUS SYS; San Jose, CA.
--- POSTER PAPERS --- 9.R “CMP Characteristics of Ferroelectric Film Fabri-cated by Sol-Gel Method for FRAM Applications” by Y.J. Seo, S.W. Park; DAEBUL UNIV.; Chonnan, KOREA; W.S. Lee;CHOSUN UNIV;Gwang, KOREA.
POST-CMP CLEANING 9.S “Evaluation of Benzotriazole Removal Capabilities of Several Copper Post-CMP Cleaners” by E. Walker, S. Naghshineh and D. Peters; ATMI; Bethlehem, PA.
(Invited Session)
(SESSION X -
8:15 - 10:15 A.M.
Chairman: Dr. Kausik Chatterjee 10.A “A Stochastic Algorithm for 3D Maxwell Solution Within Optical On-Chip IC Interconnects: Materially Homogeneous, Scalar Wave-Equation Benchmarks” by J. Kalyanasundharam, D. Krishna, R.B. Iverson and Y.L. LeCoz; RENSSELAER POLYTECH. INST.; Troy, N.Y.
10.B
“Modeling of Distributed Parasitic Effects and New 4-Port Equivalent
Circuit for Small Gate-Width FET Building Blocks” by S. Lee and R.
Roblin; OHIO STATE UNIV.; Cleveland, OH.
10.C “Stochastic Inductance Extraction in Digital IC Interconnect Structures at High Frequencies” by K. Chatterjee, P. Matos, S. Jahanian; CALIFORNIA STATE UNIV.; Fresno, CA.
10.D
“The Evolution of Metal Grain Size Distributions” by T.S. Cale and M.O.
Bloomfield;
RENSSELAER POLYTECH. INST.;
Troy, N.Y. 10.E “Accurate Nanometer Copper Interconnect Inductance Modeling Using Giga-Hertz Wafer Measurements” by K.J Chang; TSING HUA UNIV.; Taiwan, R.O.C.; and L. F. Chang; SEQUENCE DESIGN; Santa Clara, CA. 10.F “Modeling of Two Coupled Transmission Lines in Even and Odd Mode” by J. Diao, Y. Tretiakov, Y. LeCoz, and J.F. McDonald; RENSSELAER POLYTECH. INST.; Troy, N.Y.
--- POSTER PAPERS ---- 10.G “The Modeling of Temperature Distribution on Vertical LPCVD Furnace for Depositing Film on Deep Trench Pattern Wafer” by C. Wang; PROMOS TECH; Taiwan, R.O.C. 10.H “On the Reliability and Failure Analysis of Very Large Scale Integrated Circuits” by S. Jahanian, K. Chatterjee; CALIFORNIA STATE UNIV; Fresno, CA.
(Invited Session)
SESSION XI -
10:30 A.M. - 12:15 P.M.
Chairman: Dr. Norman Gitis
11.A
“New Findings in Eddy Current Physics in Thin and Ultra-Thin Metal Films
Provide Some Unique Capabilities for In-Line / In - Situ Real Time Thin
Film Thickness and Process State Monitoring” by Y. Gotkis, A. Owczarz,
R. Kistler, D. Hemker, R. Charatan, T.H. Lin, N. Bright’ LAM RESEARCH;
Fremont, CA. 11.B “Thickness Measurement Method of Dielectric Film on LSI Patterns Using Waveform Analysis of Multi-Spectral Reflectance” by T. Hirose, M. Nomoto; HITACHI; Yokohama, JAPAN; and T. Arai; RENESAS TECH; Tokyo, JAPAN. 11.C “CMP Process and Consumable Evaluation With PadProbe” by J. Fang, K.M. Davis; IBM; East Fishkill, N.Y.; N.V. Gitis and M. Vinogradov; CTR. For TRIBOLOGY; Campbell, CA. 11.D “Next Generation Materials for CMP Retaining Rings” by R. Moussa; GREENE, TWEED & CO; Kulpsville, PA. 11.E “Incoming Inspection of CMP Consumables at the Semiconductor Fab” by N.V. Gitis, M. Vinogradov; CTR. For TRIBOLOGY; Campbell, CA.
2003 VMIC
LUNCHEON
“THREE DIMENSIONAL INTEGRATION:
(Invited Session)
Chairman: Dr. Yuzhuo Li
12.A
“Effect
of pH on Silicon Oxide and Nitride Planarization Using Alumina/Ceria Mixed
Abrasive Slurries”
by S. Hegde and S. V. Babu; CLARKSON UNIV.; Potsdam, N.Y. 12.B “New Fujimi Slurry for Copper CMP” by S. Raider and P. LeFevre; FUJIMI CORP; Tualatin, OR. 12.C “Particle, Slurry and Pad Interaction During Copper CMP” by K. Bartosh; ATMI / ESC, Bethlehem, PA. 12.D “Slurry Component Analysis During STI Polish-ing” by W. America; IBM; East Fishkill, N.Y.; J. Keleher, and K. Rushing; CLARKSON UNIVERSITY; Potsday, N.Y. 12.E “Particle Innovations for Copper CMP” by S. Hellring; PPG; Monroeville, PA.
SESSION VIII
--- POSTER PAPERS ---
13.B
“High Via Chain Resistance Due to the Excess of Soft Sputter Etch and
Thick Titanium Layer Deposition at High Temperature” by S. Toh, K.Liu,
G. Magsamen, P. Sagarwala; ST MICROELECTRONICS; Carrollton, TX; and A.
Sidhwa; ST MICROELEC-TRONICS; Phoenix, AZ. 13.D “The Impact of Thermal Budget Causing High Via Resistance Failure for 0.18 micron Memory Products” by C. Consalvo, A. Privitera, D. Mello; ST MICROELECTRONICS;Canania; ITALY; A. Sidhwa; ST MICROELECTRONICS; Phoenix, AZ; and L. Marzaioli; APPLIED MATERIALS; Catania, ITALY. 13.E “Tungsten Via Failure and Process Optimization of Interconnect Metallization for 0.14 micron 256M DRAM” by W.P. Chiu, S. Hung, B.R. Ni, G. Ding, J. Chen; PROMOS TECH; Taiwan, R.O.C. 13.F “Improving Charging Damage to NROM Based EEPROM Device With Low Surface Charge PECVD Silicon Oxide as IMD Structure” by C.C. Lin, M.T. Lee; MACRONIX; Taiwan, R.O.C. 13.G “Understanding of the High Via Resistance Problem Due to Poor Quality of Isolation Ceramic Part” by R. Petri, L. LePrevost, L. Charrier, M.P. Nabot-Henaff; ST MICROELECTRONICS; Rousset, FRANCE; A. Sidhwa; ST MICROELECTRONICS; Phoenix, AZ.
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