SEVENTH INTERNATIONAL
CHEMICAL-MECHANICAL POLISH (C.M.P.) PLANARIZATION
FOR ULSI MULTILEVEL INTERCONNECTION CONFERENCE
(CMP-MIC) AND EXHIBITION

February 27 - March 1, 2002

CMP-MIC CONFERENCE OBJECTIVES

To assemble researchers and technical support personnel from Industry, Universities and Government Laboratories from around the globe to address all current and future issues related to CHEMICAL-MECHANICAL POLISH PLANARIZATION as applied to on-chip ULSI Multi-level Interconnection applications.

OPENING SESSION - 8:00 A.M.
Welcoming Remarks
Dr. Thomas E. Wade
General Chairman
University of South Florida

SESSION I -- 8:15 A.M.
KEYNOTE ADDRESS
SEMICONDUCTOR INDUSTRY REPRESENTATIVES:

" WHAT OUR COMPANY NEEDS FROM CMP IN THE NEAR FUTURE "

INTEL
Mansour Moinpour
Santa Clara, California

MOTOROLA
Janos Farkas
Austin, Texas

HEWLETT PACKARD
Michael Monroe
Corvallis, Orgeon

LSI LOGIC
Peter Burke
Santa Clara, California

Coffee Break 9:45 - 10 A.M.

SESSION II - 10:30 A.M. - 12 Noon
VLSI MULTILEVEL INTERCONNECTION
C.M.P. CONDUCTOR PROCESSES - Part I

Chairman: Dr. Michael Fury
EKC TECHNOLOGY
Hayward, California

--- POSTER PAPERS ---

Box Lunches - 12:00 to 12:45 P.M.

Visit Industrial Exhibitors 12:45 - 1:30 PM

SESSION III - 1:30 - 3:40 P.M.
VLSI MULTILEVEL INTERCONNECTION
CMP MODELING & SIMULATION - Part I
and CMP CONSUMABLES - Part I

CMP MODELING & SIMULATION - Part I

Chairman: Dr. Frank Kaufman
CABOT MICROELECTRONICS
Aurora, Illinois

CMP CONSUMABLES - Part I

Coffee Break 3:40 - 3:55 P.M.

SESSION IV - 3:55 - 5:05 P.M.
VLSI MULTILEVEL INTERCONNECTION
C.M.P. NOVEL APPLICATIONS

Chairman: Dr. Peter Burke
LSI LOGIC
Santa Clara, California



Thursday , February 28, 2002

SESSION V - 9 - 10 A.M.
VLSI MULTILEVEL INTERCONNECTION
CMP CONSUMABLES - Part II

Chairman: Dr. Tamba Tugbawa
M. I. T.
Cambridge, Massachusetts

Coffee Break 10 - 10:15 A.M.

SESSION VI - 10:15 - 12:15 P.M.
VLSI MULTILEVEL INTERCONNECTION
PROCESS CHARACTERICATION

Chairman: Dr. Rodney Morad
APPLIED MATERIALS
Santa Clara, California

CMP CLEANING PROCESSES


(Thursday, Lunch on Your Own, Not Provided by Conference,
Next Session Starts at 2:30 P.M.)


SESSION VII - 1:15 P.M. - 2:15 P.M.

VLSI MULTILEVEL INTERCONNECTION
DEDICATED TIME FOR CMP
POSTER PAPERS, EXHIBIT VIEWING

NOTICE TO AUTHORS OF POSTER PAPERS

Plan to put your poster up on Wednesday, Feb. 27, before 9 am at the location designated (Salon 1 - 4). Poster boards will be provided. Be available to answer questions during Session VII. Remove all posters by 3 PM Friday, Mar. 1.

SESSION VIII - 2:15 - 5:00 P.M.
VLSI MULTILEVEL INTERCONNECTION
CMP SHALLOW TRENCH ISOLATION PROCESSES

Chairman: Dr. Rod Kistler
LAM RESEARCH CORP
Fremont, California



Friday, March 1, 2002

SESSION IX - 9:00 - 10:20 A.M.
VLSI MULTILEVEL INTERCONNECTION
C.M.P. DIELECTRIC PROCESSES

Chairman: Dr. David Stein
SANDIA NAT'L LABS
Albuquerque, New Mexico

Coffee Break 10:20 - 10:35 A.M.

SESSION X - 10:35 A.M. - 12 P.M.
VLSI MULTILEVEL INTERCONNECTION
C.M.P. CONDUCTOR PROCESSES - Part II

Chairman: Dr. Kathleen Perry
CABOT MICROELECTRONICS
Aurora, Illinois

CMP-MIC LUNCHEON - 12:00 - 2:00 P.M.

" COPPER POLISHING WITH DIELECTRIC CONSTANTS LESS THAN 2.8: CHALLENGES & SOLUTIONS"

Dr. Jayanthi Pallinti
LSI LOGIC CORP.
Research & Development Division
Santa Clara, California

SESSION XI - 2:00 P.M. - 4:00 P.M.
VLSI MULTILEVEL INTERCONNECTION C.M.P. CLEANING PROCESSES &
CMP INSTRUMENTATION & HARDWARE
Chairman: Dr. Philip Fleming
P. H. FLEMING & ASSOC.
Colorado Springs, Colorado

CMP CLEANING PROCESSES