EIGHTH INTERNATIONAL

DIELECTRICS & CONDUCTORS FOR ULSI MULTILEVEL INTERCONNECTION
CONFERENCE & LECTURES

Monday February 25, 2002

DCMIC CONFERENCE OBJECTIVES

To assemble researchers and technical support personnel from Industry, Universities and Government Labs from around the globe to address all current and future issues related to Dielectrics & Conductors for on-chip ULSI Multilevel Interconnection applications.

OPENING SESSION - 8:15 A.M.

  • Welcoming Remarks
    Dr. Thomas E. Wade
    General Chairman
    University of South Florida

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  • SESSION I -- KEYNOTE ADDRESS
    "RECENT DEVELOPMENTS IN LOW-K,
    NANOPOROUS ORGANOSILICATE DIELECTRICS "
    Dr. Willi Volksen
    IBM ALMADEN RESEARCH CENTER
    San Jose, California

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    Coffee Break 9:00 A.M. - 9:15 A.M.

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    SESSION II - 9:15 A.M. - 10 A.M.
    VLSI MULTILEVEL INTERCONNECTION
    TOPICAL LECTURE - #1

    "ADVANCES IN ULTRA LOW-k DIELECTRIC MATERIALS"

    Dr. Chiu H. Ting
    UNITED MICROELECTRONICS CORP.
    San Jose, California

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    SESSION III - 10 A.M. - 12 P.M.
    VLSI MULTILEVEL INTERCONNECTION
    DIELECTRICS MATERIAL ISSUES: Part I

    • Chair: Dr. Robert Miller
    IBM ALMADER RES. CTR.
    San Jose, California

    • 3.A "Preparation of Low-k Porous Silica Film Incorporated With Ethylene Group" by Yasutaka Uchida and Takashi Katoh; TEIKYO UNIV. of SCIENCE & TECH.; Yamanashi, JAPAN.

    • 3.B "Characterization of SiH4/SiF4 Based on Low-k Film" by Wenxian Zhu, Cong Do, Jason Tian and Zia Karim; NOVELLUS SYSTEMS, INC.; San Jose, CA.

    • 3.C "Applications of Low-Oxygen and High Temperature Hot Plate to SiLK Cure Process in Dual Damascene Copper Interconnection" by Hiroyasu Matsugai, Masanobu Ikeda, Atsuhiro Tsukune and Takahiro Kimura; FUJITSU LTD.; Mie-ken, JAPAN.

    • 3.D "Shallow Trench Isolation High Density Plasma Chemical Vapor Deposition Oxide Gapfill for 0.1 micron and Beyond in CMOS Technology" by Z. H. Huang, Y. H. Chen, J. C. Lu, C. Y. Fu, S. M. Jang, C. H. Yu and M. S. Liang; TAIWAN SEMI. MFG. CO; Taiwan, R.O.C.

    • 3.E "A Study of Spin-On-Glass Films With Different Baking Time" by Don-Dar Lee, Li-Yeh Chou, Yi-Yueh Chen and Phileo Lu; MACRONIX INT'L CO.; Taiwan, R.O.C.

    • 3.F "Characterization of Ultraviolet Transparent Films for FLASH Devices" by Tai-Peng Lee and C. Jang; MOSEL VITELIC CORP.; San Jose, CA. and Qiang Zhao; KLA-TENCOR; San Jose, CA.

    DCMIC LUNCHEON - 12:30 - 1:30 P.M.
    " HIGH k DIELECTRICS: PROCESSING, PROPERTIES
    AND IMPLICATIONS FOR BACK-END INTEGRATION"
    Dr. Jeff F. Roeder
    ATMI MATERIALS
    Danbury, Connecticut

    SESSION IV
    VLSI MULTILEVEL INTERCONNECTION
    DIELECTRICS MATERIAL ISSUES
    AND CONDUCTOR MATERIALS
    Part II

    1:30 P.M. - 2:15 P.M.

    DIELECTRIC MATERIAL ISSUES: Part II

    Chairman Dr. Neil H. Hendricks,
    ATMI MATERIALS
    San Jose, California

    • 4.A "Tailored High Density Process Shallow Trench Isolation Process for High Aspect Ratio Gap Fill" by Hua Ji, Chuck Jang, Ching-Hwa Chen; MOSEL VITELIC CORP; San Jose, CA.

    • 4.B "Low-k Etch Stop Layer Development for 0.13 micron and Beyond for Copper Dual Damascene Integration" by C. C. Ko, T. I. Bao, L. P. Li, L. J. Li, S. M. Jang, C. H. Yu and M. S. Liang; TAIWAN SEMI. MFG. CO; Taiwan, R.O.C.
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    SESSION V - 2:15 - 3:00 P.M.
    VLSI MULTILEVEL INTERCONNECTION
    TOPICAL LECTURE - #2

    "RELIABILITY IN ULSI COPPER SYSTEMS"

    Dr. Stefan Hau-Riege
    UNIVERSITY OF CALIFORNIA
    Lawrence Livermore National Laboratory
    Livermore, California
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    Coffee Break 3:00 P.M. - 3:15 P.M.

    SESSION VI - 3:15 P.M. - 5:30 P.M.
    CONDUCTOR MATERIALS

    • 6.A "Three Dimensional LSI Chip Stacking With Through Copper Electrode in Silicon Wafer" by M. Hoshino, H. Yonemura, M. Tomisaka, T. Fujii, M. Sonohara, Y. Tomita, Y. Yamaji, T. Sato and K. Takahashi; A. S. E. T.; Ibaraki, JAPAN. Invited Paper (30 minute presentation).

    • 6.B "Killer Defect Detection in the Dual Damascene Copper Wire Process Integration" by Man-ping Cai; APPLIED MATERIALS, INC.; Santa Clara, CA.

    • 6.C "Electrical Properties of CMOS Devices with Copper Local Interconnects" by Haolu Xie, Daisy Tan, Shin Yi Lim, Chunxiang Zhu, Won Jong Yoo and Byung-Jin Cho; NAT'L UNIV. of SINGAPORE; SINGAPORE. Invited Paper (30 minute presentation).

    • 6.D "Electromigration Short-Line Effects in Copper Dual - Damascene Interconnects" by Stefan Hau-Riege; LAWRENCE LIVERMORE NAT'L LABS; Livermore, CA. and Christine Hau-Riege; AMD; Sunnyvale, CA. Invited Paper (30 minute presentation).

    • 6.E "Process Method for Integration of RF Passive Component into Copper and Black Diamond Interconnect" by Qian Yin, Doan My, Li Chao Yong, Wu Shaoyu, Kang Joon Mo, Zhang Yi and Foo Pang Dow; INSTITUTE of MICROELECTRONICS; SINGAPORE.