NINETEENTH  INTERNATIONAL
VLSI MULTILEVEL
INTERCONNECTION

 CONFERENCE
November 19 - 20, 2002
ADVANCE PROGRAM

 Tuesday, November 19, 2002
OPENING SESSION --- 9 A.M.

 Welcoming Remarks by the General Chairman
Dr. Thomas E. Wade
 University of South Florida 

SESSION I  --- 9:15 A.M.
 KEYNOTE ADDRESS

 ADVANCED INTERCONNECT -
IT’S A MATERIAL WORLD

Dr. Gene Banucci
Chairman & Chief Executive Officer
ATMI, Inc.
 Danbury, Connecticut

 

 Coffee Break 9:45 - 10:00 A.M.

SESSION II - 10:00 A.M. - 12:00 P.M.
VLSI MULTILEVEL INTERCONNECTION
DIELECTRIC SYSTEMS - Part I

          Chairman:          Dr. Neil Hendricks
             ATMI MATERIALS
             San Jose, California

2.A  “Local Nanodeposition of Dielectric Materials for Microelectronics” by H.D. Wanzenboeck, S. Harasek and E. Bertagnolli; VIENNA UNIV. of TECHNOLOGY; Vienna, AUSTRIA.
 (Invited Paper)
2.B  “Frequency Dependent Dielectric Constant of Polymer Low-k Thin Films of Nanometer Thickness” by S. W. Lee, and F. G. Shi; UNIV. of CALIFORNIA; Irvin, CA. and B. Zhao, SKYWORKS SOLN.; Newport Beach, CA.
2.C “Evaluation of Low-k Porous Silica Films Incorporated With Ethylene Groups” by Y. Uchida and M. Oikawa; TEIKYO UNIV. of SCIENCE & TECH.; Yamanashi, JAPAN
2.D “Optimization of Alignment Tree and Overlay Monitoring of Copper Low-k Dual Damascene Interconnect Layers” by N. Singh, S.S. Mehta, M. Mukerjee-Roy, R. Kumar; INST. of MICRO-ELECTRONICS; Singapore
2.E “Synthesis and Characterization of Low Dielectric Constant Nanoporous Silica From Hydrogen Silsesquioxane Oligomers” by W.C. Liu, W.C. Chen; NAT’L TAIWAN UNIV.; Taiwan, R.O.C.
(Invited Paper)
2.F

“Structural and Defect Characterization of Porous Organic Low-k Dielectrics” by T.K. Goh, T.K.S. Wong and V. Ligatchev; NANYANG TECH. UNIV.; Singapore; and S. Wu; INST. of MICROELECTRONICS; Singapore; and L. Chan; CHARTERED SEMI. MFG.; Singapore.
 


--- POSTER  PAPERS---

2.G

 “Plasma-Assisted Silicon Oxyfluoride Film Process Development and Surface Analysis for Advanced Interconnect Application” by P.S. Naidu, R. G. Krishnan, L. S. Yong, K. Nyunt, R. T. Wynn and P. Hing; INST. of MICROELECTRONICS; Singapore.
2.H “Chemical Compatibility and Electrical Reliability of Ultra Low Dielectric Constant Materials” by S. W. Lee, H.K. Kim, Y.C. Lin, Y.N. Kuo and F.G. Shi; UNIV. of CALIFORNIA; Irvine, CA.
2.I “Investigation of Sub-Atmospheric Chemical Vapor Deposition O3-TEOS USG, BPSG, PSG and Plasma Enhanced Chemical Vapor Deposition PSG Film as Sacrificial Layer in a Micro-Fluid Dispenser Device” by M.T. Lee, P. Huang, M. Chang, Y.Y. Chen; MACRONIX INT’L CO.; Taiwan, R.O.C.

 

LUNCHEON
Tuesday, Nov 19;  12:00 - 12:45 P.M.

 Luncheon  Presentation
(12:45 - 1:10 PM)

“Silicon - Germanium Alloys:
The Road From Strained Silicon MOS-FETS to On-Chip Optical Interconnects”

Mayank T. Bulsara
AMBERWAVE SYSTEMS CORP.
Salem, New Hampshire

 

 

SESSION III - 1:10 - 3:30 P.M.
 VLSI MULTILEVEL INTERCONNECTION
 VMI CMP PROCESSES

 

           Chairman:          Dr. David Stein
                                      SANDIA NAT’L LABS
                                      Albuquerque, New Mexico

 

CMP COMPLETE PROCESSES

3.A “Low-Pressure Chemical Mechanical Polishing for 300 mm Wafer Damascene Copper/Low-k Process” by S. Kondo; SEMICONDUCTOR LEADING EDGE TECH. (Selete); Ibaraki, JAPAN
 (Invited Paper)
3.B “Copper - Low-k Chemical Mechanical Planarization Gains Momentum” by S. Chadda; SPEEDFAM-IPEC; Chandler, AZ.  
(Invited Paper)
 

CMP DIELECTRIC PROCESSES
3.C “Shallow Trench Isolation: The Silent Challenge” by D. J. Stein; SANDIA NAT’L LABS; Albuquerque, N.M.
(Invited Paper)
3.D “Fixed Abrasive Chemical Mechanical Planarization on Shallow Trench Isolation Planarization for Logic Applications Beyond 0.13 microns Technology Node” by Z.H. Lin, A. Yu, C. R. Hsu, S.H. Hsu, F. Yang, T.C. Tsai and W.Y. Hsieh; UNITED MICROELECTRONICS CORP; Taiwan, R.O.C.  
3.E “Direct STI CMP With Ceria Based Slurry for 90 nm Technology” by F. Chen, S.K. Wang, C.G. Lim, H.H. Chen; CHARTERED SEMI; Singapore; and A. Lau, R. Lee and E. Goh; APPLIED MATERIALS;  Singapore; and D.L. Butler; NANYANG TECH. UNIV.; Singapore
3.F “A Study of Novel High Selectivity Slurries for Direct Shallow Trench Isolation CMP Processes” by C.P. Hou, C.Y. Fu, T.C. Tseng, Y.H. Chen, S. M. Jang and M. S Liang; TAIWAN SEMI. MFG. CO. (TSMC); Taiwan, R.O.C.
 

--- POSTER  PAPERS ---
3.G “Organic Additives for High Selectivity Oxide CMP Based on Ceria Slurry” by J.J. Kim and M. C. Kang; SEOUL NAT’L UNIV.; Seoul, KOREA.
3.H “The Defectivity Improvement of CMP IMD Oxide Process in Advanced Memory Device Applications” by Y.C. Chen, Y.H. Huang, C.Y. Liu, Y.L. Hsieh, Y.Y. Chen, T.K. Chen, T.K. Liu, L.K. Chou and V.H.H. Wang; WINBOND ELECTRONICS; Taiwan, R.O.C.; and C.J. Yang; RODEL; Taiwan, R.O.C.
 


NOVEL DIELECTRIC PLANARIZATION
3.H “New Planarization Method Assisted by Aggregated Particles Created With Optical Radiation Pressure” by K. Kimura; SONY EMCS CORP; Tokyo, JAPAN; and T. Miyoshi, Y. Takaya and S. Takahashi; OSAKA UNIV.; Tokyo, JAPAN.

Coffee Break 3:30 - 3:40 P.M.

 SESSION IV - 3:40 - 5:20 P.M.
VLSI MULTILEVEL INTERCONNECTION
 CONDUCTOR SYSTEMS


           Chairman:          Dr. Rakesh Kumar
                                     INSTITUTE of MICROELECTRONICS
                                      Singapore

4.A “Direct Electroless Plating of Copper on Metal-Nitride Diffusion Barriers” by S. Shingubara, Z. Wang, H. Sakaue and T. Takahagi; HIROSHIMA UNIV.; Hiroshima, JAPAN.  (Invited)
4.B “Copper and SiLK Integration for 0.13 micron Devices” by X.T. Chen, Y.T. Tan, Y.W.Chen, C.Y. Li, R. Murthy, Balakumar and P.D. Foo; INSTITUTE of MICRO-ELECTRONCS; Singapore. 
4.C “Review of Advanced Copper Interconnection Process - Deposition of Low Resistance and Low Stress Copper Interconnection Layer”  by T. Hara; HOSEI UNIV.; Tokyo, JAPAN.   (Invited)
4.D “Characterization of Low Temperature Copper Film Deposition by Photo-Assisted Chemical Vapor Deposition” of Y.L. Wu; NAT’L CHI-NAN UNIV; Taiwan, R.O.C.; M.H. Hsieh, K.C. Huang and H.L. Hwang; NAT’L TSING-HUA UNIV.; Taiwan, R.O.C.
4.E “Stress Effects on the Properties of Copper Layer Employed in the Multilevel Interconnection” by S. Balakumar, R. Kumar; INST. of MICROELECTRONICS; SINGAPORE; and Y. Shimura, K. Namiki, H. Tioda and T. Hara; HOSEI UNIV.; Tokyo, JAPAN 
 

 

--- POSTER  PAPERS --- 
4.F “Investigation of Electroplating and Annealing Conditions for 130 nm Copper and Black Diamond Damascene Architecture” by C.H. Seah and C.Y. Li; INST. of MICROELECTRONICS; SINGAPORE. 
4.G “Methods for Depositing Thick Aluminum Interconnect Lines by Using Multiple Aluminum Physical Vapor Depostion Chambers” by A. Sidhwa, M Goulding, L. Dion, S. Guisinger, S. English and T. Gandy; S T MICRO-ELECTRONICS; Phoenix, AZ.
4.H “The X-Ray Diffraction Data (XRD) Comparison for WCVD Nucleation Layer” by B. Ni, C.S. Huang, J. Chen and W.P. Chiu; PROMOS TECH.; Taiwan, R.O.C. 
4.I “Selective Electroplating of Copper Interconnection Layer for Liquid Crystal Display” by S. Kamijima, T. Hara; HOSEI UNIV.; Tokyo, JAPAN; and M. Kado, S. Aomori and Y. Yamamoto; ADV. LCD TECH. CTR; Yokohama, JAPAN.
4.J “Novel Copper Seed Layer Deposition for ULSI Metallizaton” by Y.W. Huang, H. D. Chang and F. S. Huang; NAT’L TSING-HUA UNIV.; Taiwan, R.O.C.
4.K “Self-Annealing Phenomena in the Copper Inter-connection” by H. Toida, Y. Shimura and T. Hara; HOSEI UNIV.; Tokyo,  JAPAN.


Wednesday, November 20, 2002 

SESSION V - 8:45 - 10:05 A.M.
VLSI MULTILEVEL INTERCONNECTION
ANALYSIS/METROLOGY & TEST STRUCTURES

  

          Chairman:          Dr. Jian-Qiang (James) Lu &
                         Dr. Ronald Gutmann
                         RENSSELAER POLYTECHNIC INST.
                         Troy, New York

 

5.A “Integrated Multiscale Process Simulation” by T.S. Cale, M.O. Bloomfield, Y.H. Im, J. Seok, C.P. Sukam and J.A. Ticky; RENSSELAER POLYTECH. INST.; Troy, N.Y.
 (Invited Paper)
5.B “Axisymmetric Chemical-Mechanical Polishing Process Model by Boundry Element Method” by T. Yoshida; YNT  CORP.; Yamaguchi, JAPAN.
5.C “Back-End-of-the-Line Thin Film Metrology Issues and Solutions for 100 nm and Beyond” by A. R. Srivatsa, S. Krishnan, J. Estabil; KLA-TENCOR CORP.; San Jose, CA.
5.D “A Sum Over Paths Impulse Response Moment Extraction Algorithm for IC Interconnect Networks: Verification, Uncoupled RC Lines” by Y.L. LeCoz, D. Krishna and G. Hariharan; RENSSELAER POLYTECH. INST.; Troy, N.Y.; K. Chatterjee; CALIFORNIA STATE UNIV; Fresno. CA.; and D.M. Petranovic, W.M. Loh and P. Bendix; LSI LOGIC CORP.; Milpitas, CA.
 

 

--- POSTER  PAPERS ---
5.E “Three Dimensional Electromigration Simulation in Copper Low-k Multilevel Interconnects” by V. Sukharev; LSI LOGIC CORP.; Milpitas, CA.
(invited Poster)
5.F “VCO for 5 Gigahertz in Copper Low-k Process” by T. Tong and M. Doan; INST. of MICROELECTRONICS; SINGAPORE.
5.G “A Floating Random-Walk Algorithm for IC Inter-connect Analysis: Theory & Two Dimensional Skin Effect Verification” by K. Chatterjee; CALIFORNIA STATE UNIV.; Fresno, CA.; and Y.L. LeCoz; RENSSELAER POLYTECH. INST.; Troy, N.Y.
5.H “Probe Tip Dependency in Atomic Force Microscopy Process Metrology” by S. Wang, M. B. Yu and C. Y. Li; INST. of MICROELECTRONICS; SINGAPORE; and J. C. H. Phang; NAT’L UNIV. of SINGAPORE; SINGAPORE.
5.I “ The Increasing Value of Metrology” by T. Boynton and M. Narasimhan; KLA-TENCOR; San Jose, CA.
5.J “Yield Analysis of Cross-Bridge Kelvin Via Resistors” by  A. Krishnamoorthy, X. Bu and Q. Guo; INST. of MICRO-ELECTRONICS; Singapore.
5.K “Integrated Analytical Technologies - Role and Relevance in Copper Oxidation Resistance and Microelectronics Application” by R. G. Krishnan; INST. of MICRO-ELECTRONICS; Singapore.

 

Coffee Break 10:05 - 10:20 A.M. 

 

SESSION VI - 10:20 A.M. - 12:00 Noon
VLSI MULTILEVEL INTERCONNECTION
RELIABILITY & BARRIERS

 

          Chairman:          Dr. Loren W. Linholm
                         NAT’L INST. of STD. & TECH. (NIST)
                         Gaithersburg, Maryland

 RELIABILITY ISSUES

 

6.A “Yield/Reliability Improvement of Multilevel Inter-connect Using Sampling Directed Layout Modifications” by G. A. Allan; UNIV. of EDINBURGH; Edinburgh, UNITED KINGDOM.
6.B “Impact of Via and Upper Layer Formation on Electromigration Failure Mechanism of Lower Layers in Dual-Damascene Copper Interconnects” by Q. Guo, A. Krishnamoorthy, N.Y. Huang, M.L. Shirley and P.D. Foo; INST. of MICROELECTRONICS; Singapore.
6.C “The Leakage Current Study of Copper/Xerogel Damascene Structure With Nano-Cluster TaSix Barrier” by C.H. Chen, C.P. Chang, M.S. Tsai and F. S.  Huang; NAT’L TSING-HUA UNIV.; Taiwan, R.O.C.
 

 

--- POSTER  PAPERS ---
6.D “Failures in Physical Vapor Deposition Aluminum Plugs Due to Hydrogen Anneal and Final Test Bake Process Steps” by A. Sidhwa, M. Kalaga, M. Goulding, T. Gandy, P. Leonardi, A. Ravaglia and R. Sampson; S T MICRO-ELECTRONICS; Phoenix, AZ.
6.E “Yield Enhancement in Copper / SiLK Dual Damascene Interconnect Process by Optimization of Via Etch and Wet Clean” by M.B. Ramana, C.K. Chang, X. T. Chen, M. Mukherjee-Roy, Y.T. Tan; INST. of MICRO-ELECTRONCIS; Singapore.
6.F “A Study on the Quantification of Post-Etching Polymer Removal by Wet Chemical Cleaning in Dual Damascene Process” by C.K. Chang and M. B. Ramana; INST. of MICROELECTRONICS; Singapore.
6.G “Substrate Line Defect Induced by Backend Thermal Stress” by Y.Y. Chang, J.N. Peng, K.Y. Tseng, S.L. Chou, T.J. Hong and W.C. Lien; MACRONIX INT’L CO.; Taiwan, R.O.C.
6.H “A Case Study - Resist Poisoning in Copper and Low-k Dual Damascene Process” by S.S. Mehta, M. Mukherjee-Roy, N. Singh and R. Kumar; INST. of MICRO-ELECTRONICS; Singapore.
6.I “Polymers Removal of Deep Trench Etch Process for Copper Low-k RF Inductors” by K.P. Yap, V.N. Bliznetsov, C.K. Chang, M.B. Yu and A.Y. Du; INST. of  MICROELECTRONICS; Singapore.
 

 

BARRIER/CONTACT/ADHESION LAYERS
6.J “Study of Ultrathin Tantalum Diffusion Barrier for Copper Interconnect Systems” by B.K. Lim, H.S. Park, S.W. Woo; NANYANG TECH. UNIV.; Singapore; and K. H. See, and C.S. Seet; CHARTER SEMI.; Singapore.
6.K “Advanced Low Pressure Source (ALPS) Cobalt Deposition and Silicidation for Sub - 0.13 micron Devices” by V. Fortin, K.C. Wu and C.H. Chen; MOSEL VITELIC CORP.; and M. Khan, K. Yoon, C. Jiang and C. Cha; APPLIED MATERIALS; Santa Clara, CA.
 

 

--- POSTER  PAPERS ---
6.L  “Reduction in Contact Resistance by Using a Modified Barrier Process and Understanding the Step Coverage Limitations Using an Evolve Simulation Program” by A. Sidhwa, T. Gandy, M. Goulding and C. Spinner: S T MICRO-ELECTRONICS; Phoenix, AZ.; and V. Prasad and T. Cale; RENSSELAER POLYTECH. INST.; Troy, N.Y.
6.M “Integrity of Ultrathin TiN Diffusion Barrier by Atomic Layer Deposition for Copper Metallization” by S.W. Woo, H. S. Park, B. K. Lim; NANYANG TECH. UNIV.; Singapore; and H.J. Kim; HYNIX SEMI.; Cheongju, KOREA.
6.N “Nano-Cluster Ta - Si Diffusion Barrier” by D. W. Lin, L.S. Ke and F.S. Huang; NAT’L TSING-HUA UNIV.; Taiwan, R.O.C.
6.O “Characterization of Alpha - Ta Diffusion Barrier for Copper Metallization” by Z.L. Yuan, D.H. Zhang, C.Y. Li, K. Prasad, C.M. Tan, P.W. Lu, R. Kumar and P.D. Foo; NANYANG TECH. UNIV.; Singapore
6.P “Comparison of Titanium Liner Quality of Self - Ionized Plasma IMP and Collimator” W. Lian, C.S. Huang, J. Chen, W.P. Chiu; PROMOS TECH. INC.; Taiwan, R.O.C.
6.Q “A New Method for Deposition of Cubic Ta Diffusion Barrier for Copper Metallization” by Z.L. Yuan, D.H. Zhang, C.Y. Li, K. Prasad, C.M. Tan; NANYANG TECH. UNIV.; Singapore; and L.J. Tang; INST. of MICRO-ELECTRONICS; Singapore.

 

 

2002 VMIC LUNCHEON

Wednesday, November 20;  12:00 - 12:45 P.M.

Luncheon  Presentation
(12:45 - 1:10 PM)

“LOW-k DIELECTRICS FOR THE
90 NANOMETER NODE AND BEYOND”

Dr. Devendra Kumar
ASM CORP.
 San Jose, California

 

 

 

SESSION VII  -  1:10 - 2:05 P.M.
VLSI MULTILEVEL INTERCONNECTION
POSTER PAPER / EXHIBITION
DEDICATED  VIEWING  TIME

 

SESSION VIII - 2:05 - 3:25 P.M.
VLSI MULTILEVEL INTERCONNECTION
CMP PROCESSES

          Chairman:               Dr. Seiichi Kondo
                                          SELETE
                                          Ibaraki-ken, JAPAN

 

CMP CONSUMABLES

8.A “Chemically Enhanced Copper Polishing With Abrasive-Free “Micelle Slurry” by H. Takahashi, M. Tsurugaya, T. Matsuda and K. Miyazaki; ASAHI KASEI CORP; Kanagawa, JAPAN; and T.K. Doy; SAITAMA UNIV.; Saitama, JAPAN.
8.B “Evaluation of Two Types of Barrier CMP Slurries for Copper Low-k Materials” by S. Balakumar, T. Selvaraj, L.B. Fu, C.Y. Li and R. Kumar; INST. of MICRO-ELECTRONICS; Singapore.
 


--- POSTER  PAPERS ---
8.C “Padprobe for Quantitative Control of Pad Surface Conditions and Wear” by N. Gitis, M. Vinogradov, A. Meyman, J. Xiao; CTR. for TRIBOLOGY; Campbell, CA
8.D “A Preliminary Study of Gentle CVDD Pad Dressers, Potential for Fixed Abrasives Conditioning” by M.H. Chan, M.H. Wang and C. C. Teng; KINIK CO.; Taiwan, R.O.C.
8.E “An Overview of Fixed Abrasives for Chemical Mechanical Polishing” by K. Teo, J. Gagliardi and J. Kollodge; 3M COMPANY; Singapore
8.F “Handling Characteristics of a Ceria-Based STI CMP Slurry in Vacuum - Pressure Dispense Slurry Delivery System and a Pump Loop” by R. Singh and B. Roberts; BOC EDWARDS; Santa Clara, CA.; P. Chelle, P. Berar and B. Small; EKC TECH.; Hayward, CA.; and G. Conner; MYKROLIS CORP.; Billerica, MA.
8.G “Cost Reduction of Tungsten CMP by Using Slurry Dilution in Foundry Production” by F. Fang, C.J. Huang and L.H. Chen; UNITED MICROELECTRONICS CORP; Taiwan, R.O.C.
8.H “A Development of Super High-Pressure Micro Jet System for Pad Dressing and Post - CMP Cleaning in CMP Process” by Y. Seike, S. Kawashima and K. Miyachi; ASAHI SUNAC CORP.; Aichi, JAPAN; and T.K. Doy; SAITAMA UNIV.; Saitama, JAPAN.
 


CMP CONDUCTORS
8.I “Electrical and Topographical Effect of Different Oxide Dummy Densities and Structures on Copper CMP” by W. W. Leow, K. Pak and H.S. Park; NANYANG TECH. UNIV; Singapore.
8.J “Copper CMP: Transition From 130 nm Initial Applications to the Challenges of 90 nm and Ultra Low-k Integration” by J. Chee, J. Chamberlain, S. Wang, P. Feeney and M. Peterson; CABOT MICROELECTRONICS; Singapore.
 (Invited Paper)
 


--- POSTER PAPERS ---
8.K “ Study of Electro-Chemical Mechanical Polishing for Copper Damascene Process” by T. Fujita, O. Kinoshita and A. Isobe; TOKYO SEIMITSU CO; Tokyo, JAPAN; and T. Doy; SAITAMA UNIV.; Saitama, JAPAN.
8.L “The Relationship Between End-Point Detecting of Tungsten CMP and Tungsten Film” by C.Y. Yen, C.H. Hung, J. Chen, C.S. Huang; PROMOS TECH. CO; Taiwan, R.O.C.
8.M “Effect of Different Barriers Polishing on Dishing and Erosion During Copper CMP” by S. Balakumar, T. Selvaraj, L.B. Fu, C.Y. Li and R. Kumar; INST. of MICROELECTRONICS; Singapore; and L. P. Chye; NAT’L UNIV. of SINGAPORE.

 

Coffee Break - 3:25 - 3:40 PM

 

SESSION IX  - 3:40 - 5:00 P.M.
VLSI MULTILEVEL INTERCONNECTION
 PACKAGING/CMP HARDWARD  & PROCESSING

 

          Chairman:       Dr. Kausik Chatterjee
                                  CALIFORNIA STATE UNIVERSITY
                                  Fresno, California

 

3-D PACKAGING & NANOPHOTONICS

9.A “Processing Technology for High Density Multifunctional Integration (HDMI) Using Wafer Bonding and Monolithic Inter-Wafer Interconnection” by J.Q. Lu, Y. Kwon, A. Jindal, K.W. Lee, J. McMahon, B. Rajagopalan, A.Y. Zeng, R.P. Kraft, J.F. McDonald, T.S. Cale and R.J. Gutmann; RENSSELAER POLYTECH. INST.; Troy, N.Y.; and B. Altemus, B. Xu, E. Eisenbraun and J. Castracane; UNIV. of ALBANY; Albany, N.Y.
 (Invited Paper)
 
9.B “Nanophotonics: Optical Waveguides, Optical Switching and Advances on Photonic Interconnection” by E. S. Kong; INST. of MICROELECTRONICS; Singapore.
 (Invited Paper)
 


--- POSTER PAPERS ---
9.C “Microprocessor Power Management Integration by VRB-CPU Approach” by X. Zhang, A.Q. Huang and F. C. Lee; VIRGINIA POLYTECH. INST.; Blacksburg, VA.
9.D “Synergy Between Three Dimension Stacking and ADP Wafer Thinning” by S. Savastiouk and P. Halahan; TRU-SI TECH; Sunnyvale, CA.
 


CMP HARDWARE
9.E “CMP Removal Profile Capability Via Multi-Zone Polishing Head & Advanced Process Control” by S. Huey, C. Garretson, J. Qian, B. Lusher, S. Mear, H.  Fang, A. Nickles and R. Tolles; APPLIED MATERIALS; Santa Clara, CA.
(Invited Paper)
 


--- POSTER PAPERS ----
9.F “Leading Edge CMP Head Development for Excellent Polishing Planarity & Uniformity Using Solo Pad” by S. Yamada, K. Tanaka, M. Numoto, A. Yamane and A. Isobe; TOKYO SEIMITSU CO; Tokyo, JAPAN.
 


VMI PROCESSING

9.G “Middle Stop Layer Recess Study in Dual Damascene Via Etch Process” by H. Cong, W.P. Liu, J.X. Li, Y.R. Pradeep, C.H. Low, W.J. Liu, E.P. Yu, B.C. Zhang, A. Cutherbertson and J.B. Tan; CHARTERED SEMI. MFG.; Singapore.
 


--- POSTER PAPERS ----
9.H “Optimization of Photoresist Stripping for OSG Low-k Copper Damascene Technology” by V.N. Bliznetsov, Y.J. Su and C.F. Tsang; INST. of MICROELECTRONICS; Singapore.
9.I “In-Situ Corner Rounding During Contact Etching for Improved Plug Fill” by D.C. Liu, J. K. Lu, S. S. Hwu and A. J. C hiou; MACRONIX INT’L; Taiwan, R.O.C.
9.J “Reactive Ion Etching of Ultra Deep Super-Vias in Dielectric Films for Three Dimensional Chip Integration” by R. Murthy, B.M. Mukherjee-Roy, C.C. Kuo and R. Kumar; INST. of MICROELECTRONICS; Singapore.
9.K “To Improve Uniformity of Thermal Budget and Film Quality in Batch Type Process by Adding In-Situ Anneal” by P. Lin, J. Lee, A. Ku, J.F. Wang and S. Chang; PROMOS TECH; Taiwan, R.O.C.
9.L “Resist Re-Flow Process for Trench Shrink in Dual Damascene” by S. Sathappan, M. Mukherjee-Roy and N. Singh; INST. of MICROELECTRONICS; Singapore.

 

SESSION X
VLSI MULTILEVEL INTERCONNECTION
DIELECTRIC SYSTEMS - Part II

 

--- POSTER PAPERS ----

10.A “Study on the Thermal Stability of Porous SiLK” by L.Y. Yang, D.H. Zhang; NANYANG TECH. UNIV.; Singapore; and P.D. Foo, C.Y. Li and W. Shaoyu; INST. of MICROELECTRONICS; Singapore
10.B “A Study on Surface Roughness on the Via Side-Walls in Low-k Organic Polymer Film Etching” by R. Murthy, C. C. Kuo; INST. of MICROELECTRONICS: Singapore.
10.C “To Improve Thickness Uniformity in PE CVD TEOS Process Using LP Ozone TEOS As Seasoning Layer” by J. Lee, H.L. Chung, A. Ku, J.F.Wang, S. Chang; PROMOS TECH.; Taiwan, R.O.C.
10.D “Critical Issues in the Integration of Copper Inter-connects With Black Diamond” by X. Bu, A. Krishnamoorthy, Y. J. Su; INST. of MICRO-ELECTRONICS; Singapore.
10.E “Annealing Influence on Defects and Atomic Structure of Porous Organic Low-k Dielectrics” by V. Ligatchev, T.K. Goh, T.K.S. Wong, Rusli; NANYANG TECH. UNIV.; and S. Wu, L. Chan; INST. of MICRO-ELECTRONICS; Singapore.
10.F “Effects of Gas Composition and R.F. Power on the Properties of SiCO:H Low-k Dielectric Films” by B. Narayanan and R. Kumar; INST. of MICRO-ELECTRONICS. Singapore.

  

 NOTICE TO AUTHORS OF POSTER PAPERS 

Plan to put ALL posters for ALL SESSIONS up on Tuesday, November 19, before 9:30 am at the location designated (Check at Conference Registration Desk). Poster boards will be provided as indicated in author kits. Be available AT YOUR POSTER  to answer questions during Session VII (from 1 - 2 pm on Wednesday, Nov. 20).  Plan to remove your poster on Wednesday afternoon from 3 - 4 pm. All posters are to be down for room clean-up by 4 pm on Wednesday, Nov. 20.