To assemble researchers and technical support personnel from Industry, Universities and Government Laboratories to address all current and future issues related to ULSI Multilevel Interconnection systems.

TOPICAL AREAS 

• THIS YEAR’S EMPHASIS: Copper / Ultra-Low-k Systems, C.M.P. , Packaging, Reliability, Optical Sys.

• CONDUCTOR SYSTEMS (copper interconnects, advanced barriers, organometallics, integrated optics, superconductors, conducting polymers, refractory/noble & other materials, etc.)

• DIELECTRIC SYSTEMS ( ultra-low-k & high-k materials, inorganic and organic, interlevel or passivation)

• RELIABILITY, FAILURE/YIELD ANALYSIS, MATERIAL COMPATIBILITY STUDIES

• PLANARIZATION ISSUES (C.M.P., processing techniques,  integration, manufacturing, equipment)

• NOVEL PACKAGING/3-D SYSTEMS (wafer level packaging, 3-D system on a chip, vertical integration)

• MODELING AND SIMULATIONS (process, equipment, test structures, performance)

A 300 - 400 word abstract with supporting tables/graphs/photos which clearly describes the nature, scope, content, organization and key points of the proposed paper are required for paper selection and session assignment.   The name, title and affiliation of authors, complete with return address, telephone and  fax numbers, e-mail address of principal contact should appear on the first page and the paper title and author’s name on each subsequent page.  Mail, E-mail or fax a copy of the abstract to be received by SEPTEMBER 25, 2002. Authors will be notified of paper acceptance with instructions for publication by Oct. 1, 2002.  Manuscripts are due in final form for publication in the official VMIC Conference Proceedings by Oct. 21, 2002 (to be available at the meeting). Please obtain clearance prior to sending.