• 2.A "Fill of 0.35 Micron Contact Structures Using Silver Forcefill" by M.G.M. Harris, P. Rich and N. Rimmer; TRIKON TECH.; Newport, UNITED KINGDOM.

• 2.B "In-Situ Monitoring of Copper - Damascene Electro-chemical Plating Solutions" by P. M. Robertson, ATMI; San Jose, CA. (Invited Paper)

• 2.C "The Optimum Content of Mg in Electroless Silver Plating for Microelectronic Interconnection" by H.H. Park, S. H. Cha; SEOUL NAT'L UNIV.; Seoul, KOREA; C.D. Lee, J.J. Kim; LG PHILLIPS LCD; Kyong, KOREA.

• 2.D "Void-Free Cu Filling of 0.05 to 0.10 Micron Inter-connections " by U. Cohen, G. Tzanavaras; JETS TECHNOLOGY; Santa Clara, CA.

• 2.E "Comparison of Options for Sub 0.10 Micron Generation Damascene Copper Feature Fill" by D. Smith, T. Archer, E. Webb, J. Sukamto, J. Reid; NOVELLUS SYSTEMS; Wilsonville, OR; T. Andryushchenko, M. Danek, E. Klawuhn, R. Rozbicki, T. Suwwan de Felipe; NOVELLUS; San Jose, CA; and A. Frank; SEMATECH; Austin, TX. (Invited Paper)

• 2.F "The Enhancement of Adhesion Strength, Reduction of Stress and Suppression of Agglomeration in ULSI Copper Interconnection" by T. Hara; HOSEI UNIVERSITY; Tokyo, JAPAN. (Invited Paper)

• 2.G "Stress Free Copper Electropolishing" by P.H. Yih, D. H. Wang, S. H. Chiao; ACM RESEARCH; Fremont, CA.

• 2.H "Deuterium Post - Metallization Anneal of Copper Film" by Y.L. Wu, Y. C. Hwang; NAT'L CHI-NAN UNIV.; Taiwan, R.O.C.; J.K. Lan and Y.L. Wang; T.S.M.C.; Taiwan, R.O.C.

• 2.I "The Impact on Tungsten Deposition Uniformity Due to Collapse of the Purge Ring on WxZ Tungsten Heaters" by M. Gonsalves, A. Sidhwa, K. Dennis, T. Gandy; ST MICROELECTRONICS; Pheonix, AZ.

• 2.J "SiH4 Post Flow Effect Between Tungsten Chemical Vapor Deposited Nucleation Process and Bulk Deposition Process" by W. P. Chiu, C. S. Huang and B.R. Ni; PROMOS TECH.; Taiwan, R.O.C.

• 2.K "Deposition of Low Stress and Low Resistivity Copper Conductive Layers by Electroplating Employing Copper-Hexafluoro-Silicate Electrolytic Solution" by T. Hara, K. Miyazawa; HOSEI UNIV.; Tokyo, JAPAN; and M. Miyamoto, T. Yonezawa, S. Ishida; MORITA CHEMICAL; Osaka, JAPAN.

NOTE: Winners of Industrial DOOR PRIZES will be announced at 1:45 P.M. on Wednesday afternoon, September 26, in the Exhibit Hall. Only conference registered attendees who are present are eligible to win door prizes.

• 4.A "Reducing CMP Process Cycle Time While Maintaining Yield With Automated Process Control" by J. Moyne, A. Cheng; UNIV. of MICHIGAN; Ann Arbor, MI; J. Colt, J. Chapple-Sokol, R. Nadeau, P. Smith; IBM MICRO-ELECTRONICS; Essex Jct., VT.; and B. Van Eck; INT'L SEMATECH; Austin, TX. (Invited Paper)

• 4.B "Nano-Topography Affects on CMP Planarization Performance" by M. Tsujimura, H. Matuso; EBARA; Tokyo, JAPAN; and M. Ota; TOKYO METROPOLITAN UNIV.; Tokyo, JAPAN. (Invited Paper)

• 4.C "Quantitative Functional Testing on CMP Materials Using A Bench-Top CMP Tester With Multiple Sensors" by N. Gitis, M. Vinogradov; CENTER FOR TRIBOLOGY; Campbell, CA.
  --- POSTER PAPER ---

• 4.D "Preliminary Study of Endpoint Detection for Chemical Mechanical Planarization Processes Using Acoustic Emission" by H. Hocheng, Y. L. Huang; NAT'L TSING HUA UNIV; Taiwan, R.O.C.
  CMP MODELING & SIMULATION

• 4.E "Modeling of Pattern Dependencies in Abrasive-Free Copper Chemical Mechanical Polishing Processes" by T. Tugbawa, T. Park, B. Lee, D. Boning; M. I. T.; Cambridge, MA.; P. Lefevre; INT'L SEMATECH; Austin, TX.; and J. Nguyen; SPEEDFAM-IPEC, Phoenix. AZ. (Invited Paper)

• 4.F "Numerical Analysis to Study the Effect of Turbulence on the Particles in Chemical Mechanical Planarization Processes" by W. Jeng; ASIA IC; Taiwan, R.O.C.; and J. J. Yeuan, S.H. Lin; FENG CHIA UNIV.; Taiwan, R.O.C.

• 4.G "A Multiscale Contact Mechanics and Hydrodynamics Model of Chemical Mechanical Polishing" by A.T. Kim, J. A. Tichy and T. S. Cale; RENSSELAER; Troy, N.Y.
  --- POSTER PAPERS ---

• 4.H "Anti-Lubrication Behavior of Copper CMP" by H. Liang, G.H. Xu; UNIV of ALASKA; Fairbanks, AK.

• 4.I "A Critical Particle Reynolds Number Analysis of Brush Scrubbing" by G. Burdick, N. Berman, S. Beaudoin; ARIZONA STATE UNIV.; Tempe, AZ.

• 5.A "An Effective Technology Using SiCN / FSG Structures for Dual Damascene Copper Process" by N. Miura, J. Noguchi, K. Oomori, T. Jimbo, H. Aoki and T. Tamaru; HITACHI; Tokyo, JAPAN.

• 5.B "Deposition and Characterization of Ionized PVD Ta and TaN Barrier Films for Copper Interconnects" by S.R. Burgess, K. Buchanan and J. Cresswell; TRIKON TECH.; Newport, SOUTH WALES

• 5.C "Critical Challenges and Newly Emerging Directions in Diffusion Barrier Technology by G. Ramanath; RENSSELAER POLYTECH; Troy, NY (Invited Paper)
  --- POSTER PAPERS ---

• 5.D "Process Integration of Via Etch Stop in TiN for Advanced CMOS Technology" by Q. Li, F.H. Gn, H. M. Li, H. Cong, A. See; CHARTERED SEMI; SINGAPORE.

• 5.E "CVD / PVD Copper Seed Layer for Sub 0.10 Micron Inteconnects" by U. Cohen; U.C. CONSULTING; Palo Alto, CA.

• 5.F "A Study of Silicon Carbides Doped With Oxygen and Nitrogen" by Z.H. Huang, T.I. Bao, S.M. Jang, C.H. Yu and M.S. Liang; T.S.M.C.; Taiwan, R.O.C.

• 5.G "Performance of Tantalum Diffusion Barrier in the Cu / Ta / SiO2 / Si Multilayer Structure" by K.M. Latt, H.S. Park, Y.K. Lee; NANYANG TECH UNIV.; SINGAPORE; and H.L. Seng, L. Rong; NAT'L UNIVERSITY OF SINGAPORE.

• 5.H "Influence of Sputtering Tool on Ti Thin Film Formation" by C.F. Lo, C. Tsai, P. Gilman; PRAXAIR SURFACE TECH; New York, N.Y.; and B. Wang; U.M.C.; Taiwan, R.O.C.
  DIELECTRIC SYSTEMS

• 5.I "A Novel Method to Form Porous CVD Oxide Film" by C.T. Ni, E. Su, A. Liu and K. Tsai; T. S. M .C. ; Taiwan, R.O.C.
  --- POSTER PAPERS ---

• 5.J "Metrology for Control of Near-Planar Shallow Trench Structures via Atomic Force Microscopy" by M.E. Lagus; IBM MICROELECTRONICS; Hopewell Jct.; N.Y. and S.M. Hand; DIGITAL INST; Santa Barbara, CA.

• 5.K "Development of a High Deposition Rate Process for Borosilicate Glass Films" by M. Patel and S. Govindarajan; INFINEON TECH; Richmond, VA.

• 5.L "Metal-Insulator-Metal Capacitors for RF BiCMOS Technology" by M. C. Olewine, K.F. Saiz and R. Dondero; PHILIPS SEMI; Albuquerque, N.M.

• 5.M "Method to Reduce HDP Oxide Thickness Variations at Narrow and Wide Trenches" by T.P. Lee and C. Jang; MOSEL VITELIC; San Jose, Ca.

• 5.N "Electrical Characteristics of Methyl-Doped CVD Low-k Dielectrics" by L.J. Li, C.C. Ko, T.I. Bao, Y.C. Lu, S.M. Jang, C.H. Yu and M.S. Liang; T. S. M. C.; Taiwan, R.O.C.

• 5.O "Optimization of Remote Plasma Clean for SACVD BPSG and BSG Process" by A. Jain; UNIV. of VIRGINIA; Charlottesville, VA; and S. Govindarajan; INFINEON TECH.; Sandston, VA.

• 5.P "A Study of SOG Film With Different Baking Time" by D.D. Lee, L.Y. Chou, Y.Y. Chen and P. Lu; MACRONIX; Taiwan, R.O.C.

• 6.A "Design of Experiments Methods Used for Chemical Mechanical Planarization of Shallow Trench Isolation for a Multi-Response System" by L. Tinoco; INTEL; Portland, OR; and M. Melloch; PURDUE UNIV.; W. Lafayette, IN.

• 6.B "High Selectivity Slurry for STI CMP" by E. S. Oswald, R. Her; FERRO ELECTRONIC MAT'L; Penn Yan, N.Y.

• 6.C "Chemical Mechanical Polishing of Porous Low-k Films: Single Damascene Schemes and Related Issues" by K. Wijekoon, Y. Moon, F. Redeker, A. Demos, N. Bekiaris and T. Weidman; APPLIED MATERIAL; Santa Clara, CA.

• 6.D "Chemical Mechanical Planarization of SiLK for Copper Damascene and ILD/STI Applications" by R. Her, D. Duncan and B. Edelbach; FERRO ELECTRONIC MAT'L; Penn Yan, N.Y.
  --- POSTER PAPERS ---

• 6.E "Comparison of Dow Chemical's SiLK and Porous SiLK Dielectric Resins Using Cabot Microelectronics Barrier Slurries" by J. Hawkins, S. Wang, G. Grover, M. Peterson, J. Chamberlain and R. Foster; CABOT MICRO-ELECTRONICS; Aurora, IL.; and M. Simmonds, G. Myers; DOW CHEMICAL; Midland, MI.

• 6.F " Global Planarization of Direct STI-CMP Process Using High Selectivity Slurry" by C.B. Kim, Y. J. Seo; DAEBUL UNIV.; Chonnam, KOREA; and S.Y. Kim; ANAM SEMI; KOREA.

• 6.G "Chemical Mechanical Polishing of CVD Low-k Films: A Comparison of Selective and Non-Selective Processes" by K. Wijekoon, Y. Moon, F. Redeker, T. Pan, M. Naik and L.Q. Xai; APPLIED MATERIALS; Santa Clara, CA.

• 6.H "Optimization of Polishing Pad Set for Direct STI-CMP Applications" by S.W. Park, Y.J. Seo; DAEBUL UNIV.; KOREA.; S.Y. Kim; ANAM SEMI; KOREA.

• 6.I " Direct Polish STI With Reflexion Fixed Abrasive Web" by A. Nickles, G. Leung, V. Mohan, H. Tam, P. McReynolds, G. Prabhu and T. Osterheld; APPLIED MATERIALS; Santa Clara, CA.

• 7.A "Optoelectronics Packaging Challenges" by J.J. Stankus; NORTEL NETWORKS; Richardson, TX.

• 7.B "Packaging Challenges of MEMS Components" by T.C. Chai, C.S. Premachandra, S.C. Chong, M.K. Iyer; INST. of MICROELECTRONICS; SINGAPORE.

• 7.C "Test and Wirebond Challenges for Fine Pitch, Low-k Dielectric and Copper Bond Pads" by J. Kister, F. Keller and M.G. Osborne; KULICKE & SOFFA; Milpitas, CA.

• 7.D "Wafer Process of Through Electrode in Si Wafer Using Copper Damascene for Three Dimensional System on Chips" by M. Hoshino, H. Yonemura, M. Tomisaka, T. Fujii, M. Sunohara, K. Takahashi; ASET.; Ibaraki, JAPAN

• 7.E "Packaging Copper Based Semiconductors (Electroless-Nickel/Gold for Solder Bumping and Wirebonding) by A.J.G. Strandjord and S. Popelar; I.C. INTERCONNECT: Colorado Springs, CO.
  --- POSTER PAPERS ---

• 7.F "Rapid Reliability Assessment of ULSI Electronics" by P. McCluskey; UNIV. of MARYLAND; College Park, MD.

• 7.G "A New Concept on Low Cost Plastic Packaging for GHz Devices" by K. Seyama, S. Kikuchi, M. Nishihara, H. Yamamoto; FUJITSU LTD; Kanagawa, JAPAN.

• 7.H "FEM Simulation of Microwave Field Inside an Oven for Curing of Underfill Packaging" by S.Yi, L. Liu and C.K. Sin; NANYAG TECH. UNIV.; SINGAPORE.

• 7.I "Structure, Characterization and Reliability of Thick Film Capacitors Embedded in the Low Temperature Cofired Ceramics (LTCC)" by S.C. Lin, Y.T. Chen and S.Y. Chang; I.T.R.S.; Taiwan, R.O.C.

• 8.A "Effect of Temperature on Thermoanalytical Properties of Polishing Pads" by A. Tregub, M. Moinpour and J. Sorooshian; INTEL CORP; Santa Clara, CA.

• 8.B "Optimization of Chemical Mechanical Planarization From the Viewpoint of Consumable Effects" by J. Luo and D. Dornfeld; UNIV. of CALIFORNIA; Berkeley, CA. (Invited Paper)

• 8.C "Surfactant Behavior and Study in Slurry" by B.T. Lin, C.S. Chen, W.K. Yeh; TSMC.; Taiwan, R.O.C.

• 8.D "Evaluation of Mixed Abrasive Slurry Systems for Copper and Oxide Polishing" by A. Jindal, S. Hegde and S.V. Babu; CLARKSON UNIV.; Potsdam, N.Y. (Invited Paper)

• 8.E "Tribology, Fluid Dynamics and Removal Rate Characterization of Novel Slurries for ILD Polish Applications" by A. Philipossian; UNIV. of ARIZONA/INTEL CORP; Tucson, AZ. (Invited Paper)
  --- POSTER PAPERS ---

• 8.F "Pad Hydration and CMP Removal Rates" by D. Castillo-Mejia, S. Gold, V. Burrows and S. Beaudoin; ARIZONA STATE UNIV.; Tempe, AZ.

• 8.G "Surfactant Interaction With Copper CMP Slurries" by S. Sundaram, X. Gao, U.R. Murthy, C.S. Magee, R.K. Pinschmidt; AIR PRODUCTS & CHEMICALS; Allentown, PA; J.A. Siddiqui; DUPONT AIR PRODUCTS; Tempe, AZ

• 8.H "The Effect of Alumina Abrasive Particle Size and Crystalline Type on Tungsten CMP Polish Results" by J.B. Wang, K. Sheu, J. Chen, T.Y. Lo, Y.H. Kung, C.M. Lin, T. Tsai; NANYA TECH; Taiwan, R.O.C.; T. Maw, B. Tredinnick; EKC TECH.; Hayward, CA.

• 8.I "Concentration Limits When Measuring CMP Slurries Using a Non-Invasive Back Scattering With Cell Position Control" by J. Westbrook, X. Shi, P. Davis and Y. Li; CLARKSON UNIV.; Potsdam, N.Y.

• 8.J "Chemical Mechanical Polishing Using a Lubricating Boundary Layer" by C.J. Molnar; BEAVER CREEK CONCEPTS; Wilmington, DE.
  CMP CONDUCTOR PROCESSES

• 8.K "Platinum Chemical Mechanical Polishing for FRAM Fabrication" by H. Wang, R. Schmidt, C. Ye and S. Lane; RODEL; Newark, DE.

• 8.L "Copper CMP for Ultra Low-k Intermetal Dielectric" by T. Shih, C.W. Chung, S.N. Lee, S.M. Jang, C.H. Yu and M.S. Liang; TSMC.; Taiwan, R.O.C. (Invited Paper)

• 8.M "Direct Observation of Chemical Interactions Between Copper and Polyurethane Surfaces in Water" by H.Liang; UNIV. of ALASKA; Fairbanks, ALASKA; and T. LeMogne, J.M. Martin; ECOLE CENTRALE de LYON; Lyon, FRANCE.

• 8.N "Copper CMP of Low-k Dielectrics With Linear Planarization Technology" by A. J. Jin, S. Srivatsan, S. Jew, K.Y. Ramanujam, P. Cheng, R. Kistler; LAM RESEARCH; Fremont, CA. and I. Vos; IMEC; BELGIUM.
  --- POSTER PAPERS ---

• 8.O "Chemical Mechanical Polishing of Copper/Low-k Dual Damascene" by C.W. Chung, T. Shih, S.M. Jang, C.H. Yu and M.S. Liang; TSMC.; Taiwan, R.O.C.

• 8.P "H2O2 and APS Reactive Liquids for Copper CMP" by J. Keleher, S. Waud, G. Bain and Y. Li; CLARKSON UNIV.; Potsdam, N.Y.

• 8.Q "SEM & EDX Analysis of Plug Dense and Iso Area of Different WCMP Overpolish Time on 300 mm Pattern Wafers" by C.N. Huang, M. Lin, J.Y. Wu; UNITED MICROELECTRONICS CORP; Taiwan, R.O.C.

• 8.R "Evaluation of Polishing Pads and Slurries for Tungsten Damascene CMP" by K.C. Wu, D. Lui and C.H. Chen; MOSEL-VITELIC; San Jose, CA.; and B. Koutny, G. Lou, I. Gilboa and S. Geha; CYPRESS SEMI.; San Jose, CA.

NOTE: Winners of Industrial DOOR PRIZES will be announced at 1:45 P.M. on Wednesday afternoon, September 26, in the Exhibit Hall. Only conference registered attendees who are present are eligible to win door prizes.

• 10.A "New Methodologies for Interconnect Reliability Assessments of Integrated Circuits" by S. P. Hau-Riege; INTEL CORP; Hillsboro, OR.; and C.V. Thompson; M. I. T.; Cambridge, MA. (Invited Paper)

• 10.B "The Mechanism Behind Superconformal Electro-deposition of Copper: Model and Experiment for Trenches Down to 75 nm Wide" by D. Josell, T. Moffat, D. Wheeler and W. Huber; NIST.; Gaithersburg, MD.

• 10.C "Reliability Studies of Multilevel Interconnection With Intermetal Dielectric Air Gaps" by V. Sukharev, R. Choudhury, C. W. Park; LSI LOGIC; Santa Clara, CA.; and B.P. Shieh, K. C. Saraswat; STANFORD UNIV.; Stanford, CA.

• 10.D "Integrated Multiscale Process Simulation of Electro-chemical Deposition of Copper" by M. O. Bloomfield, S. Sen, K. E. Jansen and T.S. Cale; RENSSELAER POLYTECH.; Troy, N.Y.(Invited Paper)

• 10.E "Optimum Interconnect Design for ASIC Chips" by P. Zarkesh-Ha, B. Loh, P. Bendix; LSI LOGIC; Milpitas, CA; and J. C. Meindl; GEORGIA TECH; Atlanta, GA.

• 10.F "A Feature Scale Model for Atomic Layer Deposition" by M.K. Gobbert; UNIV. of MARYLAND; Baltimore, MD.; and V. Prasad, M.O. Bloomfield and T.S. Cale; RENSSELAER POLYTECH; Troy, N.Y.
  --- POSTER PAPERS ---

• 10.G "Stress Modelling of Stresses in Multilevel Interconnect Schemes" by A. Mathewson; N.M.R.C.; Cork, IRELAND; and C. Gonzales, M. De Oca, S. Foley; CYPRESS SEMI; Cork, IRELAND.

• 10.H "Modeling and Simulation Opportunities for 3D Integrated Circuits" by V. Prasad, M.O. Bloomfield, J. Lu, O. Klaas, A. Maniatty, Y. LeCoz, M.S. Shepard and T.S. Cale; RENSSELAER POLYTECH; Troy, N.Y.

• 10.I "Process Capability Optimization" by J. J. Flaig; APPLIED TECH; San Jose, CA.

  10.J "A New Dirichlet-Neumann Random-Walk Algorithm for Electromagnetic Analysis of IC Interconnects: ID Verification, Materially Homogeneous Domains" by K. Chatterjee, R.B. Iverson and Y.L. LeCoz; RENSSELAER POLYTECH; Troy, N.Y.

  CONDUCTOR SYSTEMS - PART II

• 10.K "Production Control Using Optoacoustics for Fast, In-Line Copper Metrology" by M. Gostein, J. Tower and C. Moore; PHILIPS ANALYICAL; Natick, MA. (Invited Paper)

• 10.L "Design and Fabrication of Damascene Patterned Interconnections for "Face-to-Face" Wafer Bonded 3D-Stacked IC Via Chain Test Structures" by J.Q. Lu, O. Erdogan, Y. Kwon, P. Belemjian, G. Rajagopalan, D.L. Bae, C.K. Hong, R.P. Kraft, T.S. Cale, J.F. McDonald and R.G. Gutmann; RENSSELAER POLYTECH; Troy, N.Y.; and B. Xu, E.T. Eisenbraun and J. Castracane; STATE UNIV. of NEW YORK; Albany, N.Y. (Invited Paper)
  --- POSTER PAPERS ---

• 10.M "Co-Suppression Behavior of Polyethylene Glycol and Chloride Ion at Copper Electrodeposition" by Y. S. Kim, S.K. Kim and J.J. Kim; SEOUL NAT'L UNIV; Seoul, KOREA.

• 10.N "Extending Copper Electroplating to 0.035 Micron Manufacture Node" by P.H. Yih, D.H. Wang and S.H. Chiao; ACM RESEARCH; Fremont, CA.

• 10.O "Etching and Cleaning at the Bevel and Side-Wall by Chemical Spin Etching in Copper Interconnection Si Wafer" by T. Hara, T. Taniguchi; HOSEI UNIV.; Tokyo, JAPAN; K. Kinoshita; SEZ JAPAN; Tokyo, JAPAN; H.Q. Li, J. Takamura; RAYTEX; Tokyo, JAPAN; and T.C. Bristow; CHAPMAN INSTRUMENTS; Rochester, MA.

• 11.A "Temperature Accelerated AC Electrical Soft Break-down of Low-k Thin Films: Thickness Dependence" by F.G. Shi; UNIV. of CALIFORNIA; Irvine, CA; and B. Zhao; CONEXANT SYSTEMS; Newport Beach, CA. (Invited Paper)

• 11.B "Effects of Copper Diffusion on MOSFET Electrical Properties" by C. Zhu and W.J. Yoo; NAT'L UNIV. of SINGAPORE; SINGAPORE.

• 11.C "Impact of Module Integation on Copper Dual Damascene Defectivity Mechanisms" by A.R. Sethuraman, S.A. Kekare and R. Yang; KLA-TENCOR; San Jose, CA. (Invited Paper)
  --- POSTER PAPERS ---

• 11.D "A Novel Method to Prevent the Aluminum Pad Crystal Like Defect With the Copper Damascene Structure" by Y.H. Shen, C.C. Chen; TSMC.; Taiwan, R.O.C.

• 11.E "The Impact of the Abnormal AlCu Grain Growth on Thick Metal Interconnect Lines Used for Wireless Chipset" by A. Sidhwa, M. Kalaga and T. Gandy; ST MICROELECTRONICS; Phoenix, AZ.

• 11.F "Spider Like Defect Correlated With Tungsten Polycide" by J. Hsieh, C.S. Huang, W.P. Chiu; PROMOS TECH; Taiwan, R.O.C.

• 11.G "Characterization of Particle Contamination Source in Reactive Sputter TiN Deposition Process" by B. Voss, J. Shen and D. Jendresky; SAMSUNG SEMI; Austin, TX.

• 11.H "Failure Analysis for Low Yield Caused by Charging Effect by CVD System for IMD Layer" by G.S. Cho, G.O. Park, Y.M. Kwon, K.H. Suh and J. Lee; ANAM SEMI; Kyunggi, KOREA.

• 11.I "The Impact of a RF Plasma Prior to Ti/TiN Deposition on the Formation of Volcanoes in Tungsten Dual-Damascene Structures for High-Density Flash Memory Applications" by V. Fortin, D. Avalos, T.P. Lee, G. Kovall, C. Jang, D. Lui and C.H. Chen; MOSEL VITELIC; San Jose, CA.

• 11.J "The Advanced Studies on Interface Between Photo Resistor and Dielectric ARC Film to Overcome Irregular Coating Spot Phenomenon" by G. Lee; PROMOS TECH; Taiwan, R.O.C.CMP - RELIABILITY ISSUES

• 11.K "Correlating Polishing and Electrical Performance of 1st Step and 2nd Step Copper CMP With Defectivity and the Impact of Filtration" by G. Vasilopoulos, A. Zamarro, Z. Lin; MYKROLIS; Bedford, MA; and K. Devriendt, M. Meuris; IMEC; Leuven, BELGIUM.
  --- POSTER PAPERS ---

• 11.L "Effect of Process Conditions on Defectivity in Abrasive Free Copper CMP" by J. Keleher, X. Shi, S. Kenney, M. Jiang and Y. Li; CLARKSON UNIV; Potsdam, N.Y.

• 11.M "Modeling of the Scratch Issues for Various CMP Types" by E. Tseng, M. Lin and J.Y. Wu; UNITED MICRO CORP; Taiwan, R.O.C.

• 11.N "An Investigation of Surface Oxide Damage Resulting From Tungsten CMP Using H2O2 As the Oxident" by D.A. Hansen, D. Watts; EBARA TECH; San Jose, CA; and G. Moloney; CYBEQ NANO TECH; San Jose, CA.

• 11.O "Ti Silicide Residue Caused S14 256M DRAM Bit Line Short Through the Watermark Formation" by B.R. Ni, C.S. Huang, W.P. Chiu; PROMOS TECH; Taiwan, R.O.C.
  CMP - CLEANING PROCESSES

• 11.P "Investigation the Two Part Cleaning Process With Semi-Aqueous Fluoride Chemistries" by R. Small, M. Carter, S. J. Kirk, M. Cernat, B. Hanson; EKC TECH; Hayward, CA. (Invited Paper)
  --- POSTER PAPERS ---

• 11.Q "Energy Aspects of Particle Removal During Post-CMP Cleaning" by H. Liang; UNIV. of ALASKA; Fairbanks, AK; Y. Wang; APPLIED MATERIALS; Santa Clara, CA.

• 11.R "Evaluation of Particle Removal Efficiency in Wafer Cleaning Process Using FlexLine Polyvinyl Alcohol Brushes" by P. Gopalan, G. Chen, Y. Epshteyn, I. Emesh and X. Yang; SPEEDFAM-IPEC; Chandler, AZ.

• 12.A "Characterization of a Silica Based STI CMP Slurry in a Vacuum-Pressure Dispense Slurry Delivery System and Pump Loop" by R.K. Singh, E.C. Kong and J.P. Bare; BOC EDWARDS; Santa Clara, CA.; and B. Johl; RODEL; Phoenix, AZ.

• 12.B "Flexible Polishing Surface vs. Rigid Polishing Surface CMP: Pros and Cons" by Y. Gotkis, D. Wei and R. Kistler; LAM RESEARCH; San Jose, CA.

• 12.C "Effective Detection of Post Oxide CMP Defect" by S.N. Peng, J. F. Jiang; T.S.M.C.; Taiwan, R.O.C.

• 12.D "Effect of CMP Slurry Filtration on Wafer Defectivity Reduction" by H. Linkowich; FILTERITE; Timonium, MD.

• 12.E "Copper CMP Process Monitoring Using an In-Line Compact Metrology System" by D. Likhachev, E. Maiken, K. Johnson, F. Stanke; SENSYS INSTRUMENTS; Santa Clara, CA; and K.Y. Ramanujam, G. Lee; LAM RESEARCH; Fremont, CA; and H. Ibuki; MARUBENI SOLUTIONS; Tokyo, JAPAN.

• 12.F "Removal Rate Distribution Dynamics" by T.R. Taylor, C.S. Xu and R. Kistler; LAM RESEARCH; Fremont, CA.