SIXTH INTERNATIONAL
CHEMICAL-MECHANICAL POLISH (C.M.P.) PLANARIZATION
FOR ULSI MULTILEVEL INTERCONNECTION CONFERENCE
(CMP-MIC) AND EXHIBITION
March 7 - 9, 2001
http://www.imic.org
CMP-MIC CONFERENCE OBJECTIVES
To assemble researchers and technical support personnel from Industry, Universities and Government Laboratories from around the globe to address all current and future issues related to CHEMICAL-MECHANICAL POLISH PLANARIZATION as applied to on-chip ULSI Multi-level Interconnection applications.
OPENING SESSION - 8:00 A.M., March 7, 2001
Welcoming Remarks
Dr. Thomas E. Wade
General Chairman
University of South Florida
SESSION I -- 8:15 A.M. KEYNOTE ADDRESS
CMP CORPORATE OFFICERS:
" OUR COMPANY'S VISION FOR CMP IN THE FUTURE "
Matthew Neville, President and CEO - CABOT MICROELECTRONICS
Tony Khouri, President & CEO - RODEL INC.
Kenneth L. Schroeder, President and CEO - KLA - TENCOR
Loyal Peterman, Jr., President & CEO - ABRASIVE TECHNOLOGY
Neels Kriek, President- BOC EDWARDS
FOLLOWED BY QUESTION & ANSWER SESSION
Moderator: Michael A. Martinez - MCA Corp.
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Coffee Break 9:45 - 10 A.M.
SESSION II - 10 A.M. - 12 Noon
VLSI MULTILEVEL INTERCONNECTION
C.M.P. MODELING & SIMULATION - Part I
Chairman: Dr. Duane Boning
MASS. INST. of TECH. (MIT),
Cambridge, Massachussetts
- 2.A "Modeling of Chemical Mechanical Planarization" by J. Luo, D. Dornfeld, Z. Mao and E. Hwang; UNIVERSITY of CALIFORNIA; Berkeley, CA.
Invited Paper
- 2.B "Modeling of Wafer Pressure Distribution and Removal Uniformity for Lip Seal Carrier" by M. Hollatz and P. Thieme; INFINEON TECH.; Dresden, GERMANY; A. Ullrich and W. Pompe; DRESDEN UNIV. of TECH.; Dresden, GERMANY.
- 2.C "CMP Wafer and Feature Scale Models: Finite Element Contact Model" by A. T. Kim, J. A. Tichy and T. S. Cale; RENSSELAER POLYTECH. INST.; Troy, New York.
- 2.D "Numerical Investigation of Particulate Flow of Slurry in Chemical Mechanical Planarization Process" by W. Jeng; ASIA IC MIC-PROCESS; Taiwan, R.O.C.; and J. J. Yeuan; FENG CHIA UNIV.; Taiwan, R.O.C.
- 2.E "Filling and Slotting for Process Uniformity Control in Copper Chemical Mechanical Polishing" by R. Tian; MOTOROLA; Austin, TX.; and X. Tang, D. F. Wong; UNIV. of TEXAS; Austin, TX.
--- POSTER PAPERS ---
- 2.F "Modeling of Pattern Dependencies in Multi-Step Copper Chemical Mechanical Polishing Processes" by T. Tugbawa, T. Park, D. Boning; M. I. T.; Cambridge, MA.; L. Camilletti, M. Brongo; CONEXANT SYSTEMS; Newport Beach, CA.; P. Lefevre; SEMATECH; Austin, TX.
- 2.G "A Die-Scale Simulation for Predicting ILD Thickness After CMP With Varying Dummy Metal Design Rules" by I. Y. Yoon, B. H. Kwon, Y. B. Park, H. H. Ryu and W. G. Lee; HYUNDAI ELECTRONICS; Cheongju-si, KOREA.
Box Lunches - 12:00 to 12:45 P.M.
Visit Industrial Exhibitors 12:45 - 1:30 PM
SESSION III - 1:30 - 3:30 P.M.
VLSI MULTILEVEL INTERCONNECTION
C.M.P. PROCESS CHARACTERIZATION
Chairman: Dr. Dale Hetherington
SANDIA NATIONAL LABS, Albuquerque, New Mexico
- 3.A "A Novel Photoresist Planarization for Deep Trench Capacitor Plate Formation of DRAM" by C. F. Wang, L. K. Chou, H. H. Wang, Y. C. Liang; WINBOND ; Taiwan, R.O.C.
- 3.B "Enabling Advanced I.C. Processes With CMP" by P. Feeney, et al; CABOT MICROELECTRONICS; Aurora, IL.
Invited Paper
- 3.C "Mechanistic Understanding of the CMP of Metals, Dielectrics and Semiconductors: What's Known and What's Not" by R. J. Gutmann, D. J. Duquette, P. S. Dutta and W. N. Gill; RENSSELAER POLYTECH. INST.; Troy, N. Y.
Invited Paper
- 3.D "Metrology Recipe Design for Chemical Mechanical Polishing" by A. S. Lawing; RODEL INC.; Phoenix, AZ.
- 3.E "Technical Advances in Chemical Mechanical Planarization" by J. Schlueter, M. Ferra, D. Trojan and S. Chadda; SPEEDFAM-IPEC; Chandler, AZ.
Invited Paper
- 3.F "Copper CMP: Defect Inspection Issues and Solutions" by A. Sethuraman; KLA-TENCOR; San Jose, CA.
Invited Paper
--- POSTER PAPERS ---
- 3.G "Rapid CMP Process Characterization Through Full Wafer Film Thickness Mapping" by Y. Xia, K. Daniell and G. Gardopee; ADE CORP.; Milpitas, CA.
- 3.H "CMP In-Situ Multi-Zone Endpoint Using Optical Metrology" by K. Kasprzyk and J. Schlueter; SPEEDFAM-IPEC; Chandler, AZ.; and M. Melonie; VERITY INST.; Phoenix, AZ.
Coffee Break 3:30 - 3:45 P.M.
SESSION IV - 3:45 - 5:05 P.M.
VLSI MULTILEVEL INTERCONNECTION C.M.P. CONDUCTOR PROCESSES - Part I
Chairman: Dr. Peter Burke
LSI LOGIC, Santa Clara, California
- 4.A "Tungsten CMP Process With On-Table Oxide Buff" by Y. F. Yan and R. Adebanjo; BELL LABS/LUCENT TECH; Orlando, FL.; and L. Schultz; CIRENT SEMI./LUCENT; Orlando, FL.
- 4.B "Copper CMP Using a Lam Teres Linear Planarization Technology" by I. Vos, M. Meuris and B. Sijmus; I.M.E.C.; Leuven, BELGIUM; and M. Stella, N. Delaney and K. Gobbin; LAM RESEARCH; San Jose, CA.
- 4.C "CMP Process Integration of a Reactive Liquid Solution for Copper Damascene Interconnects" by R. E. Barker, G. C. Mandigo, C. D. Lack; RODEL INC; Newark, DE.
- 4.D "Development of Planarization Processes for Nontraditional Materials: Noble Metals CMP" by K. Moeggenborg, V. Brusic, I. Cherian, A. N. Powell and W. Downing; CABOT MICROELECTRONICS, Aurora, IL.
--- POSTER PAPERS ---
- 4.E "Kinetics of the Reduction of Hydroxylamine on Copper" by A. T. Al-Hinai and K. Osseo-Asare; M.I.T.; Cambridge, MA.
- 4.F "High Throughput Copper CMP Process With Real-Time In-Situ Bulk Copper Thickness Monitoring" by K. Smekalin, B. Swedek, R. Bajaj, A. Zutshi, F. Redeker and G. Amico; APPLIED MATERIALS; Santa Clara, CA.
- 4.G New Alignment System (ATHENA) on W-CMP" by A. Shieh, A. Lin, T. Hung, M.C. Deng, J. Chen, Y. L. Hwang, T. H. Yang; MACRONIX; Taiwan, R.O.C.
- 4.H "The Effects of Polishing Condition on Dishing and Erosion in Copper CMP Process" by S.C. Hu, T. C. Tsai, C. L. Hsu, H. C. Chen and J.Y. Wu; UNITED MICRO. CORP.; Taiwan, R.O.C.
- 4.I "Hillock Defect Reduction on Copper CMP" by C. C. Lin, S. M. Jang, C. H. Yu and M. S. Liang; T.S.M.C.; Taiwan, R.O.C.
- 4.J "Pattern Geometry Effect and Time Dependence in the Copper-CMP" by A. Shieh, J. Chen and Y.L. Hwang; MACRONIX; Taiwan, R.O.C.
--- LATE NEWS PAPERS ---
- 4.K "In-Line Metrology for Control of Advanced Dual Damascene W. Polish Processes for Volume Production" by O. Kuhn and H. Drummer; INFINEON TECH; Dresden, GERMANY; F. Stanke; SENSYS INST.; Santa Clara, CA.
- 4.L "Copper Oxides in Cu CMP" by H. Liang, H. Xu; UNIV. of ALASKA, Fairbanks, ALASKA.
Thursday , March 8, 2001
SESSION V - 8:00 - 9:40 A.M.
VLSI MULTILEVEL INTERCONNECTION CMP CONSUMABLES - Part I
Chairman: Dr. Frank B. Kaufman
CABOT MICROELECTRONICS , Aurora, Illinois
- 5.A "Polyurethane Pad Degradation and Wear Due to Tungsten and Oxide Chemical Mechanical Polishing" by A. L. Moy, D. Hetherington and D. Stein; SANDIA NAT'L LABS; Albuquerque, N.M.; J. Cecchi; UNIV. of NEW MEXICO: Albuquerque, N.M.
- 5.B "Development of Abrasive Capsulation Pad Using Water Swellable Polymer" by H.Y. Kim, J. H. Park and H. D.Jeong; PUSAN UNIV.; Pusan, KOREA.
- 5.C "Effects of Temperature and Shear History on CMP Slurry Quality and Their Relation to Wafer Polish Performance" by M.L. Fisher, A. Misra and B. Schmidt; AIR LIQUIDE ELEC.; Dallas, TX.; and J. Norbert and W. Morrison; TEXAS INSTRUMENTS; Dallas, TX.
- 5.D "Nanosize Diamond Particles for Copper CMP" by E. Tyre, J. Keleher and Y. Li; CLARKSON UNIV.; Potsdam, N.Y.; R. Uriarte, D. Buckley; GENERAL ELECTRIC; Schenectady, N.Y.; D. Cerutti and T.Dumm; GENERAL ELECTRIC; Worthington, OH.
- 5.E "The Polishing Characteristics of Ceria-Based Slurry and Silica-Based Slurry in SRAM Devices" by B.H. Kwon, J. H. Lee, S. Kweon, S.Y. Lee, B. C. Kim, H. Y. Yoon, S. I. Lee and J. G. Lee; HYUNDAI; Cheongju-si, KOREA.
--- POSTER PAPERS ---
- 5.F "Polishing Oxide With a Single Layer Unfilled Cast Elastomer Pad" by D. Dick; MOTOROLA; South Queensferry, SCOTLAND; and P. Gorton; UNIVERSAL PHOTONICS; Folsom, CA.
- 5.G "Process Characterization of Abrasive Free Copper Polishing on Orbital and Rotational Platforms" by M. Grief, D. Trojan and K. Murella; SPEEDFAM-IPEC; Chandler, AZ.
- 5.H "Evaluation of a Point of Use Filtration System for Copper CMP Slurry" by J. Westbrook and Y. Li; CLARKSON UNIV.; and M. H. S. Tseng; CUNO INC.; Meriden, CT.
- 5.I "Correlation Between Slurry Composition and Copper CMP Non-Uniformity" by C.K. Min, C.L. Tsia, C.J. Wang and L.M. Chen; UNION CHEMICAL LABS; Taiwan, R.O.C.
- 5.J "Technical Directions and Challenges in Hard Disk Drive Substrate CMP" by S. Smith; CABOT MICROELECTRONICS Aurora, IL.
--- LATE NEWS PAPERS ---
- 5.K "Study of the CMP Performance of Surface Modified Colloidal Silica Slurries" by J. Siddiqui and A. M. Wilson; DUPONT AIR PRODUCTS; Richardson, TX.
Coffee Break 9:40 - 9:55 A.M.
SESSION VI - 9:55 - 11:15 A.M.
VLSI MULTILEVEL INTERCONNECTION
CMP CLEANING PROCESSES & CMP INSTRUMENTATION & HARDWARE
Chairman: Dr. Rod Kistler
LAM RESEARCH CORP, Fremont, California
CMP CLEANING PROCESSES
- 6.A "Ultra-Pure Electrolytic Hydrogen Water Implement for Advance Post CMP Cleaning in a Next Generation" by C.F. Wang, S.L. Lee, L. K. Chou, T.K. Chen, H.H. Wang, Y. C. Liang; WINBOND ELECTRONICS; Taiwan, R.O.C.
- 6.B "Interfacial Contact and Analysis During Post-CMP Cleaning" by H. Liang, H. Xu and J. Lee; UNIV. of ALASKA; Fairbanks, ALASKA; K. Bahten and D. McMullen; RIPPEY CORP.; El Dorado Hills, CA.
Invited Paper
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6.C "The Mechanism of Particle Removal and Brush Mechanics in Post-CMP Cleaning Applications" by K. Bahten, D. McMullen; RIPPEY CORP.; El Dorado Hills, CA.; H.Liang, E. Estragnat, T.G. Zhang and J. Lee; UNIV. of ALASKA, Fairbanks, ALASKA.
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6.D "Pad Life Optimization by Characterization of a Fund-amental Pad-Disk Interaction Property" by G. Prabhu, S. Kumaraswamy and D. Flynn; APPLIED MAT'L; Santa Clara, CA; and S. Qamar and T. Namola; ABRASIVE TECH; Westerville, OH.
--- POSTER PAPERS ---
- 6.E "Post CMP Cleaning Issues" by S.Y. Lee, J. G. Park; HANYANG UNIV.; Ansan, KOREA.
- 6.F "Megasonic Post-CMP Cleaning Using Chelating Basic Chemistry" by S. Ramachandran, A. A. Busnaina; NORTH-EASTERN UNIV.; Boston, MA; and R. Small, Z. Chen and C. Shang; EKC TECH.; Hayward, CA.
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6.G "Slurry Induced Metallic Contamination on Different Silicate Oxides by As-Deposited and Post-CMP Cleaning" by S.Y. Kim; ANAM SEMI.; KOREA; S.W. Park and Y.J. Seo; DAEBUL UNIV; Chonnam, KOREA.
CMP INSTRUMENTATION & HARDWARE
- 6.H "200mm to 300mm CMP Scale-Up: Hardware, Consumables and Process" by T. R. Taylor, C. Xu and R. Kistler; LAM RESEARCH; Fremont, CA.
--- POSTER PAPERS ---
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6.I "A New Method to Call End Point for W CMP to Avoid Tungsten Seam Exposure" by Y.F. Yan and R. Adebanjo; BELL LABS/LUCENT TECH; Orlando, FL.; M. Seputo; CIRENT SEMI; Orlando, CA.; H. Yamasaki, H. Ichihara and Y. Takahashi; EBARA CORP.; Fujisawa-shi, JAPAN.
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6.J "A Novel CMP Equipment Design for Large Diameter Wafer Planarization" by H. Kim and H. Jeong; PUSAN NAT'L UNIV.; Pusan, KOREA.
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6.K "Quantitative Evaluation of CMP Process Using A Bench Top CMP Tester With Multiple Sensors" by N. Gitis, M. Vinogradov; CTR. for TRIBOLOGY; Campbell, CA.
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6.L "Advancements in Diamond Pad Conditioner Technology: Historical Perspective, State-of-the-Art and Future Directions" by S. Qamar and T. Namola; ABRASIVE TECH; Westerville, OH.
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6.M "A Study of Multi Head CMP Tool Effect on BPSG Film for Advanced DRAM Applications" by D. A. Hansen, G. Moloney; CYBEQ NANO TECH; San Jose, CA.; D. Watts; EBARA TECH; San Jose, CA.
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6.N "Recent Advances in Endpoint and In-Line Monitoring Techniques for Chemical-Mechanical Polishing Processes" by D. L. Hetherington and D. J. Stein; SANDIA NAT'L LABS; Albuquerque, N.M.
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6.O "Optimization of Pad Conditioning on a SpeedFam-IPEC AvantGaard 676/776" by N. Korovin, S. Schultz and S. Guha; SPEEDFAM-IPEC; Chandler, AZ.
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6.P "The Effect of Carrier Oscillation on Within Wafer Non-Uniformity of CMP Removal Rate" by D. A. Hansen and G. Moloney; CYBEQ NANO TECH; San Jose, CA.
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6.Q "Diamond Pad Conditioners for In-Situ Applications in Low pH Metal CMP Slurries" by M. El-Shazly, R. Welonski and S. Qamar; ABRASIVE TECH; Lewis Center, OH.
SESSION VII - 11:15 A.M. - 1:00 P.M.
VLSI MULTILEVEL INTERCONNECTION
DEDICATED TIME FOR C.M.P. POSTER PAPERS, EXHIBIT VIEWING
(Thursday, Lunch on Your Own, Not Provided by Conference, Next Session Starts at 2 P.M.)
SESSION VIII - 2:00 - 3:40 P.M.
VLSI MULTILEVEL INTERCONNECTION C.M.P. CONDUCTOR PROCESSES - Part II
Chairman: Dr. Mansour Moinpour
INTEL CORP., Santa Clara, California
- 8.A "Copper CMP Strategies" by S Kordic, et al; ST MICRO-ELECTRONICS; Crolles, FRANCE.
Invited Paper
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8.B "Chemical Mechanical Polishing of Cu/Low-k and Cu/Ultra Low-k Layers for Advanced Semiconductor Device Fabrication" by S. Wang, G. Grover and C. Yu; CABOT MICROELECTRONICS, Aurora, IL.; and P. Lefevre; SEMATECH; Austin, TX.
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8.C "The Effect of Polishing By-Products on the Copper Removal Rate of the Copper CMP Process" by W.C. Chiou, T. Shih, S.M. Jang, C. H. Yu and M. S. Liang; T.S.M.C.; Taiwan, R.O.C.
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8.D "Linear Polishing Technology for W CMP" by H. Li, K. Y. Ramanujam; LAM RESEARCH; Fremont, CA.
--- POSTER PAPERS ---
- 8.E "The Process Window Study of Oxide Buffing After WCMP Process" by P. K. Niu, L. J. Hung, J.Y. Cheng and K.L. Young; T.S.M.C.; Taiwan, R.O.C.
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8.F "A Study of Defect Behavior on W - CMP Process" by H.S. Shih, C. R. Lin and H.B. Lu; UNITED MICROELECTRONIC;
Taiwan, R.O.C.
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8.G "Characterization of Oxide Buffing in W-CMP" by A. Shieh, J. Chen and Y.L. Hwang; MACRONIX; Taiwan, R.O.C.
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8.H "The Effects of First and Second Step Slurries on Copper CMP" by J. King, R. Jee, G. Appel and M. Sbragia; TSK AMERICA; San Jose, CA.
SESSION IX - 3:45 P.M. - 5:30 P.M.
VLSI MULTILEVEL INTERCONNECTION
DEDICATED TIME FOR C.M.P. ROADMAP DEVELOPMENT
The task is to project activities for the next 3 to 5 years in order to determine capabilities/hurdles/show-stoppers/etc. for the following CMP areas of interest:
| - Equipment | - Dielectric Processes
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| - Consumables | - Conductor Processes
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| - Model & Simulation | - Post-Clean
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| - Integration | - Distribution & Disposal
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Attendees will select which Roadmap Development Group in which they wish to participate. A Group Leader and a Scribe will be assigned the role of moderating the discussion and recording results. A summary of Roadmap findings will be reported at the CMP-MIC Luncheon on Friday, March 9.
SESSION X - 8:00 - 9:20 A.M.
VLSI MULTILEVEL INTERCONNECTION C.M.P. MODELING & SIMULATION - Part II
Chairman: Dr. Katia Devriendt
I.M.E.C. , Leuven, Belgium
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10.A "A Fixed Abrasive CMP Model" by B. Lee and D. Boning; M.I.T.; Cambridge, MA.; and L. Economikos; IBM; Hopewell Junction, N.Y.
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10.B "Addressing the Pattern Density Effects in Deposition/Etch/
CMP Process by Means of Simulations" by Valeriy Sukharev; LSI LOGIC; Santa Clara, CA.
Invited Paper
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10.C "A Modified Asperity Contact Model: Pad Deformation Effect on the WIWNU" by C.C. He, C.Y. Chiou, Y.J. Fann, W.C. Pan and C.L. Hus; CHUNG-SHAN INST.; Taiwan, R.O.C.
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10.D "A Model for Wafer Scale Variation of Material Removal Rate in Chemical Mechanical Polishing" by G. Fu and A. Chandra; IOWA STATE UNIV.; Ames, IA.
--- POSTER PAPERS ---
- 10.E "Solution and a Directional Velocity Model for High Order Erosion in Poly CMP" by Y.H. Kung, C.M. Lin and T. Tsai; NANYA TECH.; Taiwan, R.O.C.
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10.F "Finite Element Analysis of Contact Pressure in Chemical Mechanical Planarization" by Q. Liu and B. Wang; FLORIDA STATE UNIV.; Tallahassee, FL.
Coffee Break 9:20 - 9:35 A.M.
SESSION XI - 9:35 A.M. - 10:55 A.M.
VLSI MULTILEVEL INTERCONNECTION C.M.P. CONSUMABLES - Part II
Chairman: Dr. Kathleen Perry
CABOT MICROELECTRONICS, Aurora, Illinois
- 11.A "On Sedimentation and Redispersion of Abrasive Particles in CMP Slurries" by R. K. Singh, B. R. Roberts; BOC EDWARDS; Santa Clara, CA.
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11.B "H2O2 and APS Reactive Liquid Systems for Cu CMP" by J. Keleher, S. Wand, G. Bain and Y. Li; CLARKSON UNIV.; Potsdam, N.Y.
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11.C "Oxide Chemical Mechanical Planarization Pad Technology" by D. Stein, D. Hetherington; SANDIA NAT'L LABS; Albuquerque, N.M.; D. James; RODEL; Phoenix, AZ.
Invited Paper
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11.D "Evaluation of Large Particle Reduction in CMP Slurry Using Series Filtration" by H. Linkowich, T.B. Gutowski and A. Shucosky; FILTERITE ELECTRONICS; Timonium, MD.
- POSTER PAPERS -
- 11.E "Development of Conditioning Method Aided by Ultrasonic Cavitation" by H.D. Seo, H. J. Kim, H.Y. Kim and H.D. Jeong; PUSAN UNIV.; Pusan, KOREA.
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11.F "New Method to Evaluate Stacked Polishing Pad for CMP"
by S. Koizumi and K. Kato; KTECH RES.; Kanagawa, JAPAN.
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11.G "Experimental Investigation of the pH Dependence of Tungsten CMP Removal Rates in Iodate-Based Slurries" by D.J. Stein, T.P. Gaffney and D.L. Hetherington; SANDIA NAT'L LABS; Albuquerque, N.M.
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11.H "Surfactant Behavior and Study in Slurry" by B. T. Lin; T.S.M.C.; Taiwan, R.O.C.
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11.I "CMP Pad Dresser: A Diamond Grid Solution" by J. Sung; KINIK CO.; Taiwan, R.O.C.
SESSION XII - 10:55 A.M. - 11:55 A.M.
VLSI MULTILEVEL INTERCONNECTION C.M.P. DIELECTRIC PROCESSES
Chairman: Dr. Karey Holland ,br> TECHCET CORP , Phoenix, Arizona
- 12.A "Determination of Wafer Level Planarization Behavior for an Oxide CMP Process Using the MIT Test Pattern" by F.Meyer, S. Delage, W. Dickenscheid, P. Klose and G. Springer; INFINEON TECH.; Dresden, GERMANY; and J.W. Bartha; DRESDEN TECH. UNIV.; Dresden, GERMANY.
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12.B "End Point Enhancement by Reflective and Anti-Reflective Cap Layers for Oxide CMP" by J. Pallinti, J. Xie, R. Nagahara, D. Lee; LSI LOGIC; Santa Clara, CA.
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12.C "Ultra-Low Slurry Use for Oxide Chemical Mechanical Planarization Process" by C. C. Garretson, J.P. Rudd, B.J. Brown, B.Lusher, G. Bonne, R. Oshana and D. Flynn; APPLIED MATERIAL; Santa Clara, CA.
- POSTER PAPERS -
- 12.D "Effect of Retaining Ring System on the Polishing of 300 mm Oxide Wafers" by U. Malkoc, T. Harnisch, S. Rehbehn and G. Morsch; PETER WOLTERS SYS.; Rendsburg, GERMANY.
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12.E "Planarization Capability Study in Pre-Metal Dielectric CMP Processing" by F.L. Chin, G.P. Hua, A. Cuthbertson; CHARTER SEMI; Milpitas, CA.; and S. Misra, R. Adebanjo; LUCENT/BELL LABS; Orlando, FL.
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12.F "A Study on Removal Rate Control of Oxide CMP Process" by S.Y. Kim; ANAM SEMI; and C.B. Kim, Y.J. Seo; DAEBUL UNIV.; Chonnam, KOREA.
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12.G "The Use of Spreadsheets for Oxide CMP Process Control" by J. Jaso, D. Diefenderfer, T. Glynn and T. Giunta; DOMINION SEMI.; Manassas, VA
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12.H "Study of STI Polishing Defects Using 3M Fixed Abrasive Technology" by T. Buley; RODEL; Phoenix, AZ.; J. Gagliardi, E. Funkenbusch; 3M SYSTEMS; St. Paul, MN.; G. Sabde; MICRON TECH.; Portland, OR.
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12.I "CMP of ILD Device Wafers Using Ceria Oxide Slurry and New Carrier Head Techniques" by D. A. Hansen, G. Moloney, A. Reyes; CYBEQ NANO TECH; San Jose, CA.
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12.J "Quantified Defect Performance of Oxide Chemical Mechanical Planarization Slurries" by G. Bonne, C. Garretson, B. Lusher, B.J. Brown, S. Yang, J. Tang, L. Coughran, P. Ding, B. Zhang, K. Hughes, D. Flynn and R. Oshana; APPLIED MATERIALS; Santa Clara, CA.
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12.K "Study of Some CMP Related Yield Degradation Mechan-isms" by A. Maury and N. Layadi; LUCENT/BELL LABS; Orlando, FL.
CMP-MIC LUNCHEON - 12:30 - 2:00 P.M.
" CMP TECHNOLOGY: COMPETITION, PRODUCTS & MARKETS "
Drs. Robert N. Castellano,
THE INFORMATION NETWORK
New Tripoli, Pennsylvania
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CMP ROADMAP REPORTS - 1:30 - 2:00 P.M.
Leaders of RoadMap Topics (Session IX)
to Present Brief Report of Findings
SESSION XIII - 2:00 P.M. - 4:00 P.M.
VLSI MULTILEVEL INTERCONNECTION
C.M.P. SHALLOW TRENCH ISOLATION
and CONDUCTOR PROCESSING
Chairman: Dr. Fritz Redeker
APPLIED MATERIALS, Santa Clara, California
CMP SHALLOW TRENCH ISOLATION (STI)
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13.A "Evaluation of Fixed Abrasive Pads for STI Planarization" by L. Economikos, F.F. Jamin, A. Ticknor; IBM MICRO; Hopewell Junction, N.Y.; and A. Simpson; INFINEON TECH.; Hopewell Junction, N.Y.
Invited Paper
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13.B "Fixed Abrasive Technology for STI: Integration Into Teres Linear CMP Platform" by J. Boyd, R. Kistler, D. Wei; LAM RESEARCH; San Jose, CA.; T. Buley; RODEL INC.; Sunnyvale, CA.; and M. Pevny; 3M CO; St. Paul, MN.
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13.C "Development of a Direct Polish Process for Shallow Trench Isolation Modules" B.A. Bonner, A. Iyer, D. Kumar, T. H. Osterheld, A.S. Nickles and D. Flynn; APPLIED MATERIALS; Santa Clara, CA.
- POSTER PAPERS -
- 13.D "Effect of Slurry Abrasives on the Planarization Efficiency in Shallow Trench Isolation CMP" by Y.J. Noh, S.I. Lee, Y.S. Choi, J.Y. Kim, J.G. Jung, H.H. Kim, J.K. You and C.W. Nam; HYUNDAI ELEC.; Kyoungki-do, KOREA.
- 13.E "Silica-Based CMP Slurry for Direct, Shallow Trench Isolation Processing" by G. Bogush, J Chamberlain, P. Feeney, T. Johns, F. Khan, R. Romine, D. Schroeder and A. Walters; CABOT MICROELECTRONICS, Aurora, IL.
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13.F "Manufacturing Proven STI-CMP Process With Optical Endpoint System Control" by A. Shieh, W.H. Huang, J. Chen, Y.L. Hwang; MACRONIX; Taiwan, R.O.C.
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13.G "A Study of End Point Detection Measurement for STI-CMP Applications" by S.Y. Kim, H. S. Kim, Y. S. Kim, K. H Suh, J. Lee; ANAM SEMI.; Kyunggi-Do, KOREA.
CMP CONDUCTOR PROCESSES - Part III -
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13.H "Characterization of Dishing Behavior on Copper CMP for Advanced ULSI Interconnect" by H. C. Chen; UNITED FOUNDRY SER; Hopewell Jct., N.Y.; T.C. Tsai, M. S. Yang, J.Y. Wu; UNITED MICROELECTRONICS; Taiwan, R.O.C.
- 13.I "Development of Next Generation Barrier CMP Process for Copper Damascene" by H. Chou, P. Feeney, J. Hawkins, K. Moeggenborg, K. Bennett; CABOT MICROELECTRONICS, Aurora, IL.
- 13.J "Feasibility Study of Fixed Abrasive Matrix in the Cu-CMP Process" by A. Shieh, J. Chen, Y.L. Hwang; MACRONIX; Taiwan, R.O.C.
- POSTER PAPERS -
- 13.K "Step-by-Step Characterization in Cu-CMP by Using Non-Preston Slurry" by A. Shieh, J. Chen, Y.L. Hwang; MACRONIX; Taiwan, R.O.C.; S.Y. Shih, M.S. Jang, J. X. Lin; ERSO/ITRI; Taiwan, R.O.C.
NOTICE TO AUTHORS OF POSTER PAPERS:
Plan to put your poster up on Thursday, March 8, before
9 am at the location designated (Salon 1 - 4). Poster boards will be provided. Be available to answer questions during Session IV. Remove all posters by 3 PM Friday, Mar. 9.