SIXTH INTERNATIONAL
CHEMICAL-MECHANICAL POLISH (C.M.P.) PLANARIZATION
FOR ULSI MULTILEVEL INTERCONNECTION CONFERENCE
(CMP-MIC) AND EXHIBITION

March 7 - 9, 2001

Registration Information Registration Form

http://www.imic.org

CMP-MIC CONFERENCE OBJECTIVES

To assemble researchers and technical support personnel from Industry, Universities and Government Laboratories from around the globe to address all current and future issues related to CHEMICAL-MECHANICAL POLISH PLANARIZATION as applied to on-chip ULSI Multi-level Interconnection applications.

OPENING SESSION - 8:00 A.M., March 7, 2001
Welcoming Remarks
Dr. Thomas E. Wade
General Chairman
University of South Florida

SESSION I -- 8:15 A.M. KEYNOTE ADDRESS
CMP CORPORATE OFFICERS:
" OUR COMPANY'S VISION FOR CMP IN THE FUTURE "

Matthew Neville, President and CEO - CABOT MICROELECTRONICS

Tony Khouri, President & CEO - RODEL INC.

Kenneth L. Schroeder, President and CEO - KLA - TENCOR

Loyal Peterman, Jr., President & CEO - ABRASIVE TECHNOLOGY

Neels Kriek, President- BOC EDWARDS


FOLLOWED BY QUESTION & ANSWER SESSION
Moderator: Michael A. Martinez - MCA Corp.

Coffee Break 9:45 - 10 A.M.

SESSION II - 10 A.M. - 12 Noon
VLSI MULTILEVEL INTERCONNECTION
C.M.P. MODELING & SIMULATION - Part I

Chairman: Dr. Duane Boning
MASS. INST. of TECH. (MIT), Cambridge, Massachussetts

Box Lunches - 12:00 to 12:45 P.M.

Visit Industrial Exhibitors 12:45 - 1:30 PM

SESSION III - 1:30 - 3:30 P.M.

VLSI MULTILEVEL INTERCONNECTION
C.M.P. PROCESS CHARACTERIZATION
Chairman: Dr. Dale Hetherington
SANDIA NATIONAL LABS, Albuquerque, New Mexico

Coffee Break 3:30 - 3:45 P.M.

SESSION IV - 3:45 - 5:05 P.M.
VLSI MULTILEVEL INTERCONNECTION C.M.P. CONDUCTOR PROCESSES - Part I
Chairman: Dr. Peter Burke
LSI LOGIC, Santa Clara, California



Thursday , March 8, 2001

SESSION V - 8:00 - 9:40 A.M.

VLSI MULTILEVEL INTERCONNECTION CMP CONSUMABLES - Part I
Chairman: Dr. Frank B. Kaufman
CABOT MICROELECTRONICS , Aurora, Illinois

Coffee Break 9:40 - 9:55 A.M.

SESSION VI - 9:55 - 11:15 A.M.
VLSI MULTILEVEL INTERCONNECTION
CMP CLEANING PROCESSES & CMP INSTRUMENTATION & HARDWARE
Chairman: Dr. Rod Kistler
LAM RESEARCH CORP, Fremont, California

CMP CLEANING PROCESSES

CMP INSTRUMENTATION & HARDWARE

SESSION VII - 11:15 A.M. - 1:00 P.M.

VLSI MULTILEVEL INTERCONNECTION
DEDICATED TIME FOR C.M.P. POSTER PAPERS, EXHIBIT VIEWING


(Thursday, Lunch on Your Own, Not Provided by Conference, Next Session Starts at 2 P.M.)


SESSION VIII - 2:00 - 3:40 P.M.
VLSI MULTILEVEL INTERCONNECTION C.M.P. CONDUCTOR PROCESSES - Part II
Chairman: Dr. Mansour Moinpour
INTEL CORP., Santa Clara, California


SESSION IX - 3:45 P.M. - 5:30 P.M.
VLSI MULTILEVEL INTERCONNECTION
DEDICATED TIME FOR C.M.P. ROADMAP DEVELOPMENT

The task is to project activities for the next 3 to 5 years in order to determine capabilities/hurdles/show-stoppers/etc. for the following CMP areas of interest:
- Equipment - Dielectric Processes
- Consumables - Conductor Processes
- Model & Simulation - Post-Clean
- Integration - Distribution & Disposal
Attendees will select which Roadmap Development Group in which they wish to participate. A Group Leader and a Scribe will be assigned the role of moderating the discussion and recording results. A summary of Roadmap findings will be reported at the CMP-MIC Luncheon on Friday, March 9.


SESSION X - 8:00 - 9:20 A.M.
VLSI MULTILEVEL INTERCONNECTION C.M.P. MODELING & SIMULATION - Part II
Chairman: Dr. Katia Devriendt
I.M.E.C. , Leuven, Belgium

Coffee Break 9:20 - 9:35 A.M.

SESSION XI - 9:35 A.M. - 10:55 A.M.
VLSI MULTILEVEL INTERCONNECTION C.M.P. CONSUMABLES - Part II
Chairman: Dr. Kathleen Perry
CABOT MICROELECTRONICS, Aurora, Illinois

SESSION XII - 10:55 A.M. - 11:55 A.M.
VLSI MULTILEVEL INTERCONNECTION C.M.P. DIELECTRIC PROCESSES
Chairman: Dr. Karey Holland ,br> TECHCET CORP , Phoenix, Arizona
CMP-MIC LUNCHEON - 12:30 - 2:00 P.M.
" CMP TECHNOLOGY: COMPETITION, PRODUCTS & MARKETS "
Drs. Robert N. Castellano,
THE INFORMATION NETWORK
New Tripoli, Pennsylvania

CMP ROADMAP REPORTS - 1:30 - 2:00 P.M.
Leaders of RoadMap Topics (Session IX)
to Present Brief Report of Findings

SESSION XIII - 2:00 P.M. - 4:00 P.M.
VLSI MULTILEVEL INTERCONNECTION
C.M.P. SHALLOW TRENCH ISOLATION
and CONDUCTOR PROCESSING
Chairman: Dr. Fritz Redeker
APPLIED MATERIALS, Santa Clara, California

CMP SHALLOW TRENCH ISOLATION (STI)

CMP CONDUCTOR PROCESSES - Part III -


NOTICE TO AUTHORS OF POSTER PAPERS: Plan to put your poster up on Thursday, March 8, before 9 am at the location designated (Salon 1 - 4). Poster boards will be provided. Be available to answer questions during Session IV. Remove all posters by 3 PM Friday, Mar. 9.