VLSI MULTILEVEL INTERCONNECTION
STATE-OF-THE-ART SEMINAR
Friday, June 30, 2000

Registration Information Registration Form

This year's state-of-the-art SEMINAR will address those issues associated with current fundamental developments in advancing VLSI/ULSI multilevel interconnection towards greater functionality, density and speed.

It will include a review and discussion of those primary topical areas which impact todays multilevel interconnection events as well as project future direction for this critical industry.

A distinguished set of lecturers will participate in this SEMINAR, which is a MUST for all engineers, managers and tech-nicians working on VLSI/ULSI multilevel interconnection. The registration fee includes coffee breaks, luncheon and a visuals booklet.

THIS COURSE HAS LIMITED ENROLLMENT. YOU ARE HIGHLY ENCOURAGED TO ADVANCE REGISTER EARLY.

TOPICAL COVERAGE

  • I. INTRODUCTORY REMARKS - 8:35 A.M.
    Dr. Thomas E. Wade
    Seminar Chairman
    University of South Florida

  • II. METAL INTERCONNECTS:

    A. ADVANCE COPPER TECHNOLOGY DEVELOPMENTS - 8:45 A.M.
    Dr. Chiu H. Ting
    Steag - CuTek Research, Inc.
    San Jose, California

  • III. DIELECTRICS:

    ADVANCES IN LOW-k & POROUS DIELECTRICS - 9:30 A.M.
    Dr. Willi Volksen
    IBM Almader Research Center
    San Jose, California

    Coffee Break 10:15 A.M.
  • IV. THERMAL EFFECTS:

    HEAT TRANSFER IN ADVANCED INTERCONNECT SYSTEMS - 10:30 A.M.
    Dr. Kenneth E. Goodson
    Stanford University
    Stanford, California

  • V. OPTICAL INTERCONNECT:

    NEW DEVELOPMENTS IN OPTICAL INTERCONNECT - 11:15 A.M.
    Dr. Yu-Hwa Lo
    University of California

    Seminar Luncheon - 12:00 P.M.

    "THE INTEGRATION AND RELIABILITY OF LOW-k DIELECTRICS IN ULSI"
    Dr. Wei William Lee
    TAIWAN SEMI. MFG. CO. (TSMC)
    Hsinchu, Taiwan, R.O.C.

  • VI. C.M.P. PLANARIZATION:

    A. ADVANCED IN C.M.P. TECHNOLOGY - 1:45 P.M.

    Dr. Kathleen Perry
    Applied Materials
    Santa Clara, California

    B. C.M.P. MODELING AND SIMULATION DEVELOPMENTS - 2:30 P.M.
    Dr. Duane Boning
    Massachusetts Inst. of Technology
    Cambridge, Massachusetts

    Coffee Break - 3:15 P.M.

  • VII. MODELS & SIMULATION:

    GETTING YOUR INTERCONNECT ‘GOTCHA' WITH SIMULATION - 3:30 P.M.
    Dr. Andrew R. Neureuther
    University of California
    Berkeley, California

  • VIII. RELIABILITY:

    NEW RELIABILITY DEVELOPMENTS IN ULSI INTERCONNECTS - 4:15 P.M.
    Drs. Harry Rathore & Du Nguyen
    IBM Microelectronics
    Hopewell Junction, New York

  • IX. CLOSING REMARKS - 5:00 P.M.