• 2.A "Seed Layers and Cu Jet Plating for Interconnects Below 0.10 Microns" by U. Cohen; JETS TECH; Santa Clara, CA

• 2.B "Comparative Analysis and Study of Ionized Metal Plasma - Cu (IMP-Cu) and Chemical Vapor Deposition - Cu (CVD-Cu) on Diffusion Barrier Properties of IMP - TaN on SiO2" by K. Lee, L. Chaoyong, B. Narayanan, W. J. Jie, F. P. Dow; INST. OF MICROELECTRONICS; Singapore; Y.K . Lee, K. M. Latt, K.J. Hyung; NANYANG TECH UNIV; Singapore.

• 2.C "Electro Chemical Deposition of Cu on Ultra Thin Cu Seed" by D. Papapanayioutu, I. Ivanov, C.Ting; STEAG-CUTEK; San Jose, CA. (Invited Paper)

• 2.D "A New Copper Dry Etch Process for VLSI Multilevel Interconnection" by Y. Kuo and S. Lee; TEXAS A & M UNIV; College Station, TX.

• 2.E "Recent Progress of Cu - Low k Interconnects" by Y. Hayashi; NEC CORP; Tokyo, JAPAN. (Invited Paper)

• 3.A "A Radio-Frequency Quasi-SOI Power MOSFET Using CMP Technology" by S. Matsumoto, Y. Hiraoka, T. Sakai, T. Yachi; NTT TELECOMM. LAB; Kanagawa, JAPAN. (Invited Paper)

• 3.B "Multiplexed Local-Area-Network Interconnect Topologies: Design Concepts for the Post Copper/Low-k Decade" by R.J. Gutmann, J.Q. Lu; RENSSAELAER POLYTECH; Troy, NY (Invited Paper)

• 3.C "Technology and Design Challenges for Low Power and High Performance Microprocessors" by V. K. De and S. Borkar; INTEL CORP; Hillsboro, OR. (Invited Paper)

• 3.D "Interconnect Passive Components for Mixed Signal/RF Applications" by A. Kar-Roy, P. N. Sherman, B. Shen, S. Bhattacharya and P. Kempf; CONEXANT SYS; Newport Beach, CA. (Invited Paper)

• 3.E "Face to Face Wafer Bonding for 3D Chip Stack Fabrication to Shorten Wire Lengths" by J.F. McDonald, R. Kraft, J. Lu, T.M. Lu, A. Kumar, T. Cale, P. Belemjian and O. Ergodan; RENSSELAER POLYTECH; Troy, NY; and A. Kalyeros, J. Castracane; STATE UNIV of NEW YORK; Albany, NY
  --- POSTER PAPER---
• 3.F "Metal-Insulator-Metal (MIM) Capacitors Using Ta2O5 for RF-BiCMOS Technology" by M. C. Olewine, G.J. Colovos, J.F. DiGregorio, K.F. Saiz and R. Dondero; PHILIPS SEMI; Albuquerque, NM.
  Coffee Break 3:10 - 3:25 P.M.

• 4.A "Mechanical Aspects of Chemical Mechanical Polishing" by D. A. Dornfeld; UNIV CALIFORNIA; Berkeley, CA. (Invited Paper)

• 4.B "A Generalized Material Removal Model for the CMP Process" by A. Chandra and G. Fu; IOWA STATE UNIV; Ames, IA. (Invited Paper)

• 4.C "Chemical-Mechanical Polishing of Copper and SiLK in Model Alumina Slurries: Experimental and Modeling Results" by R.J. Gutmann, C.L. Borst, B. C. Lee, D.G. Thakurta, D.J. Duquette, and W.N. Gill; RENSSELAER POLYTECH; Troy, NY (Invited Paper)

• 4.D "Local Deposition of Dielectrics for the Deep Sub-Micron Range" by H. D. Wanzenboeck, S. Harasek, H. Langfischer, A. Lugstein, E. Bertagnolli, M. Gritsch, H. Hutter, C. Tomastik, J. Brenner and H. Stoeri; VIENNA UNIV of TECH; Vienna, AUSTRIA.

• 4.E "Low k Porous Silica Films Deposited by PECVD Using Polysiloxane" by Y. Shioya, K. Ohhira and K. Maeda; SPL; Tokyo, JAPAN; and H. Ikakura, T. Ishimaru and S. Ohgawara; CANON; Tokyo, JAPAN
  --- POSTER PAPERS---

• 4.F "CVD-Based Preparation of Porous Silica Films" by Y. Uchida; TEIKYO UNIV of SCI & TECH; Yamanashi, JAPAN; and S. Sugahara, M. Matsumura; TOKYO INST TECH; Tokyo, JAPAN.

• 4.G "Post - Etch Stripper Development for FLARE and HOSP Low-k Dielectrics" by J. Dunne, O. Leonte, A. George and J. Kennedy; HONEYWELL; Sunnyvale, CA; and D. Peters, J. Bayer and J. Rieker; ASHLAND-ACT; Easton, PA.

• 4.H "Design Methodology of Hard Mask Deposition for Organic Low Dielectric Constant Films" H. W. Chiou, J. H. Tsai, Y. S. Jean, C. I. Chang, S. D. Lee, C. Hsia; ERSO/ITRI; Taiwan, R.O.C.

NOTE: Winners of exhibitor door prizes to be announced on Wednesday afternoon, June 28, at 2:45 p.m. in the Exhibit Hall. Persons must be registered attendees and present to win.

• 5.A "A Viable 300 mm Copper CMP Process" by J. Mendonca, F. Hampton, D. Keenan; MOTOROLA; Austin, TX; and A. Zutshi, D. Vijay, B. Withers, S. Huey, R. Bajaj, R. Tolles, F. Redekar; APPLIED MAT'L; Santa Clara, CA. (Invited Paper)

• 5.B "The Improvement on Dual Damascene Tungsten Planarization via End-Point Signal Triggered Two-Step Polishing" by S.Y. Tai, M.C. Yang, J.F. Wang and C. Yi; PROMOS TECH; Taiwan, R.O.C.

• 5.C "Unlocking the Copper Damascene Puzzle" by R. Bajaj, F. Redeker, K. Wijekoon; APPLIED MAT'L; Santa Clara, CA.

• 5.D "Novel Tungsten CMP Process With Soft Pad and Optical Endpoint System Control" by A. Shieh, Y. Liu, J. Chen and Y.L. Hwang; MACRONIX; Taiwan, R.O.C.; and J. Chang, T. Liu and P. Tsai; APPLIED MAT'L; Taiwan, R.O.C.

• 5.E "Process Methodologies to Reduce Rework and Plug Coring in Sub-Quarter Micron Tungsten Chemical Mechanical Planarization Using H2O2 Containing Slurries" by B. Kassab, L. Witters, D. Dornisch, L. Camilletti, D. Teets, R. Li, M. Denham and R. Viswanathan; CONEXANT SYS; Newport Beach, CA.
  --- POSTER PAPERS ---

• 5.F "Copper CMP and Effect of Dummy Structures" by J.T. Pan and P. Li; APPLIED MAT'L; Santa Clara, CA.

• 5.G "Cu-CMP for Cu 2D Technology: Fundamentals" by Y. Gotkis and R. Kistler; LAM RES; Fremont, CA.
• 5.H "Defectivity Reduction in Copper CMP Process" by A. Zutshi, R. Surana, J. Tang, G. Lam, C. Garretson, R. Bajaj and F. Redekar; APPLIED MAT'L; Santa Clara, CA.

• 5.I "Development and Characterization of Tungsten CMP Process for 0.18 micron Technology with FSG/SRO Scheme" by X.B. Wang, F.L. Chin, S. Balakumar, C. W. Lai, B.Y.D. Su, C. Lin and P. Chew; CHARTER SEMI; Singapore.

• 5.J "Development of Low Cost and High Throughput W-CMP Process" by R. Lum, S. Mishra, L. Wu, S. Kumaraswamy, C. Chan and D. Groechel; APPLIED MAT'L; Santa Clara, CA.

• 6.A "Plasma Equipment Modeling for Process Design" by M. J. Kushner; UNIV of ILLINOIS; Urbana, IL. (Invited Paper)

• 6.B "Simulation and Analysis of Sputter Deposition Over Sub-Micron Features" by D. G. Coronell; REACTION DESIGN; San Diego, CA. (Invited Paper)

• 6.C "Simulations of C2F6/O2 and C2F6/CO Plasmas for Oxide Etch" by X.P. Xu and P. Schoenborn; LSI LOGIC; Santa Clara, CA.

• 6.D "Thermal Process Modeling for Multilevel Metallization" by T. Cale; RENSSELAER POLYTECH; Troy, NY. (Invited Paper)

• 6.E "Modeling Plasma Tools: Reactor and Feature Scales" by P. Stout and V. Kolobov; CFD RES; Huntsville, AL.

• 6.F "Chip-Scale Simulation of Pattern Processing: Methods, Models, Accuracy and Applications" by Y. Granik, O. Toublan, N. Cobb, E. Sahouria, T. Donnelly and T. Do; MENTOR GRAPHICS; San Jose, CA.
  --- POSTER PAPERS---

• 6.G "All-Optical Metrology for Rapid Characterization of Copper Damascene Structures" by M. Banet, M. Joffe, M. Gostein, A. Maznev and R. Sacco; PHILIPS ANALYTICAL; Natick, MA.

• 6.H "Modeling of Feature Superfilling Through the Use Leveling Agents in Copper Electroplating" by S. Soukane and T. S. Cale; RENSSELAER POLYTECH; Troy, NY.

• 8.A "Electromigration Failure Mechanisms in Dual Damascene Copper Multilevel Interconnections" by D. Nguyen and H. Rathore; IBM; Hopewell Jct.; NY.

• 8.B "The Influence of Post Etch Cleaning on the Stop Layer Damage for Dual Damascene Etch" by B.R. Young, Y.H. Chiu, M.H. Huang, H.J. Tao, C.S. Tsai and M.S. Liang; TSMC; Taiwan, R.O.C.

• 8.C "A Correlation of PECVD Oxide Film Charge to Transistor Leakage" by L. Zhang, D. Wei, W. Catabay, Y. Wang, J. Dong, S. Yoshikawa Y.L. Ho; LSI LOGIC; Santa Clara, CA. (Invited Paper)
• 8.D "Effect of Ti Salicide Process With Metal Contamination in BF2 Implants for Gate Oxide" by Y. Sueyoshi, M. Kondo, S. Saito and A. Ishihama; SHARP; Hiroshima, JAPAN.

• 8.E "Improvement in Gate Oxide Damage Using Low Temperature Ar-Preclean and IMP Ti Deposition in 0.18 micron Metallization" by H. Abdul-Ridha, D. Young, J. Yota, J. Wood, V. Ramanathan and M. Brongo; CONEXANT SYS; Newport Beach, CA.

• 8.F "Low Temperature CVD TiN Deposition Combined with N2/H2 Plasma Treatment to Prevent Al Extrusion" by Y.C. Chang, B. Wang and M. Lin; UMC; Taiwan, R.O.C.
  --- POSTER PAPERS ---

• 8.G "Impact of Degas Conditions on Via Chain Resistance for Integrated FSG IMD/Al-Cu Metallization Process" by J.N. Tu and C. T. Huang; MACRONIX; Taiwan, R.O.C.

• 8.H "The Effect of Tungsten Silicide Deposition Precursor on Thin Floating Gate Oxide Reliability and EEPROM Programming Efficiency" by K. Cherukuri and L. Nguyen; ST MICRO; Carrollton, TX.

• 8.I "Metal Defects Localization With a Novel Large Area Test Structure" by G. Magri and B. Zanderighi; ST MICRO; Agrate Brianza, ITALY.

• 8.J "Adhesion Promotion Study on 0.13 micron SiO:C:H Low-k/Copper Damascene Process" by C.C. Lin, T.I. Bao, S.M. Jang, C.H. Yu and M.S. Liang; TSMC; Taiwan, R.O.C.

• 8.K "Passivation Cracks in a Four-Level Metal Low-k Dielectric Backend Process" by M.C. Olewine, J.F. DiGregorio, G.J. Colovos, K.F. Saiz, H. Sun; PHILIPS; Albuquerque, NM.

• 8.L "A New Test Method for the Routine Plasma Damage Monitor" by A. C. Chen; WINBOND; Taiwan, R.O.C.

• 8.M "Elimination of Junction Spiking Problems by Using Pre-Clean Etch and Two Step TiN During Contact Barrier Deposition Process" by A. Sidhwa, C. Spinner, T. Gandy, J. Deng, S. Guisinger; ST MICRO; Phoenix, AZ.

• 8.N "Investigation of Aluminum Whisker Growth on Multilevel Metallization" by R.J. Chein, W.C. Lien and Y.Y. Chen; MACRONIX; Taiwan, R.O.C.

• 8.O "The Impact of Bell-Jar and Quartz Pedestal in Metal Deposition Tools" by A. Sidhwa, X. Breurec, C. Spinner, S. Zheng, K. Dennis; ST MICRO; Phoenix. AZ.

• 8.P "The Effect of Metal Layer Photo Rework to Etch Residue Formation and Solution" by Y.F. Huang, A.J. Chiou, N.T. Lian, S. S. Hwu and P. Liu; MACRONIX; Taiwan, R.O.C.

• 9.A "Oxide CMP Pattern Density Effects of FA vs. Slurry Processing" by B. Koutny; CYPRESS SEMI; San Jose, CA. (Invited Paper)
  --- POSTER PAPERS ---

• 9.B "Trace Metal Reduction inPost Oxide CMP Cleaning by Using Double-Sided Brush Scrubbing" by A. Shieh, W.H. Huang, J. Chen , Y.L. Hwang; MACRONIX; Taiwan, R.O.C.

• 9.C "Chemical Mechanical Planarization of ILD Device Wafers Using Ceria Oxide Slurry" by H.A. Hansen, G. Moloney and A. Reyes; CYBEQ NANO TECH; San Jose, CA.

• 9.D "The Optimization of Single Step STI CMP" by S.Y. Ting, K.J. Liu, J. Liang, C.C. Juan and T.J. Yin; WINBOND; Taiwan, R.O.C.

• 9.E "3 D Microstructural Simulation of Thin Film Deposition for VLSI Interconnects" by T. Smy; CARLETON UNIV.; Alberta, CANADA (Invited Paper)

• 9.F "Application of Multi-Layer Metal Process Models to Interconnect Design" by T. Ohta and K. Nishi; SELETE; Yokohama, JAPAN. (Invited Paper)

• 9.G "Effects of Crossing Under-Layer Interconnect Geometry on the Signal Integrity of Upper-Layer Interconnects" by J.K. Wee, K.W. Kwak, Y.J. Jeon, P.S. Lee, H.J. Lee, C.S. Park, S.B. Ye, D.J. Lee; HYUNDAI; Kyoungki, KOREA
• 9.H "Development of a Random-Walk Algorithm for IC Interconnect Analysis: 2D TE Benchmarks, Materially Heterogeneous Domains" by Y.L. LeCoz, K. Chatterjee and R.B. Iverson; RENSSELAER POLYTECH; Troy, NY.

• 10A "Thermal Stability Study of HDP FSG for Cu Dual Damascene Applications" by P.Y. Chang, P.R. Jeng and M. Liou; MACRONIX; Taiwan, R.O.C.

• 10B "Elimination of PR Poison by Surface Modification on Low-k CVD Materials" by S.M. Jeng, L.J. Li, B.R. Young, S.M. Jang, C.H. Yu and M.S Liang; TSMC; Taiwan, R.O.C.

• 10C "Optimization of Baking for FLARE Organic Low-k Dielectric Material" by Y. Xu, S.Y.M. Chooi, M.S. Zhou and S. Gupta; CHARTER SEMI; Singapore.
  --- POSTER PAPERS ---

• 10D "Thermal Stability Study of PECVD Carbon-Doped SiO2 Low Dielectric Constant Thin Films" by L.M. Han, N. Balasubramanian, S. Chen, X. Bu, P.D. Foo and J. Xie; INST of MICRO; Singapore

• 10E "Process Optimization and Film Characterization of Si-Rich Oxide Deposited by PECVD" by S.L. Wu and P.R. Jeng; MACRONIX; Taiwan, R.O.C.

• 10F "The Influence of Inter-Metal Dielectric and HDP Passivation Layer on Device Performance" by C.T. Ni; D. Yang, E. Su and K. Tsai; TASMC; Taiwan, R.O.C.

• 10G "Hydrogen Concentration Analysis in Sequentially Deposited Thin Films and Application of Surface Charge Analysis Techniques for Fast and Non-Destructive Characterization of PECVD Silicon Nitride" by C.Y. Wang, E.H. Lim, V.Y. Vassiliev, J.L. Sudijono, J.Z. Zheng and A. Cuthbertson; CHARTER SEMI; Singapore.

• 10H "A Study of PMD Films by Using SACVD and APCVD in AlSiCu and AlCu Metallization Processes" by Y. Y. Chen, W. C. Lien,W.C. Fu; MACRONIX; Taiwan, R.O.C.

• 10I "Electrochemical Planarization of Copper" by Y. Tian and I.I. Suni; CLARKSON UNIV; Potsdam, NY.

• 10J "Gap Filling Capability Study of LTS/Hot Al Process on Metal Damasceme" by H. Chen, S.H. Huang, S.K. Huang, Y. T. Huang and E. Chiang; WINBOND; Taiwan, R.O.C.
  --- POSTER PAPERS ---

• 10K "Improvement of FIB-Based Tungsten Metallization" by H. Langfischer, E. Bertagnolli, A. Lugstein, H.D. Wanzenbock, H. Hutter, M. Gritsch and C. Tomastik; VIENNA UNIV; Wien, AUSTRIA.

• 10L "Evolution of Aluminum Target Orientation and Its Influence on Deposition Film Uniformity at the Early Life Sputtering" by C.F. Lo, A. Snowman, R. Mathew, P. Gilman, D. Draper and C. Fisher; PRAXAIR-MRC; Orangeburg, NY.

• 10M "Metal Etch With PR-Free Process for 0.15 micron Technology" by Y.H. Chiu, M.H. Huang, H.J. Tao and C.S. Tsai; TSMC; Taiwan, R.O.C.

• 10N "X-Ray Diffraction Study of Cobalt Silicide Phases Formed by Hot Sputtering and In-Situ Anneal" by D. Saigal and G. Kohara; APPLIED MAT'L; Santa Clara, CA.

• 10O "Mechanism of Aluminum Light Spots Formation" by Y.J. Wu and M. Lin; UNITED MICRO CORP; Taiwan, R.O.C.

BARRIER/CONTACT/ADHESION LAYERS

• 11A "Barrier Layers for Cu Interconnection - Barrier Properties and CMP" by T. Hara; HOSEI UNIV; Tokyo, JAPAN. (Invited Paper)

• 11B "Very Deep M1 Contact Process Integration on W Bit Line Depending on the Different Premetal Cleaning and Barrier Metals Ti/TiN" by H. Kwon, C.Y. Kim, J. Kim, J.H. Youn, B. Eun and K. Kim; HYUNDAI; Kyoungki, KOREA.

• 11C "Low Temperature RTP Monitoring by Using Cobalt Silicide Characterisitics" by T. Tseng, R. Chang and M. Lin; UNITED MICRO CORP; Taiwan, R.O.C.

• 11D "Electrical Characteristics for Metal Contact in ULSI Interconnect Applications" by D.W. Kim, K.W. Kim, J.S. Kim, S.H. Son, S.T. Hong, W.S. Woo, C.Y. Lee, M. K. Gong, K.S. Son; HYUNDAI; Kyoungki, KOREA
  --- POSTER PAPERS ---

• 11E "Ta Sputtering Target and Sputter Deposition of Ta/TaNx Diffusion Barriers for Cu Interconnects" by H. Zhang; TOSOH SMD; Grove City, OH.

• 11F "Improved TiN Based Diffusion Barrier Using Multi-layered Ti/TiN Structure" by W.F. Wu, K. C. Tsai; NNDL; Taiwan, R.O.C.; C.G. Chao, Y.L. Chin, B. S. Chiou; CHIAO TUNG UNIV; Taiwan, R.O.C.; C.F. Huang, S.T. Wu; TSING HUA UNIV; Taiwan, R.O.C.

• 11G "Solutions of Integration Issues for Through-ARC Via Process Using MOCVD TiN as Glue Layer" by C.R. Lin, J.J. Huang, H.B. Lu, C.K.L. Wu; UNITED MICRO CORP; Taiwan, R.O.C.

• 11H "The Effect of SiH4 Soak for WCVD Process on the CVD TiN Barrier Film" by Y.K. Kim, J.W. Han, S.C. Shim, J.W. Park, Y.S. Jang, S. Y. Lee and K.H. Suh; ANAM SEMI; Kyunggi, KOREA.

• 11I "The Effects of Liners on W CMP and Plug Performance" by C.T. Ni, M. Chen and K. Tsai; TASMC; Taiwan, R.O.C.

• 11J "Effects of Argon Plasma Preclean on Non-Salicide Silicon Contact Resistance for Non-Volatile Memory" by C. T. Huang, C.Y. Lee, Y.L. Hwang; MACRONIX; Taiwan, R.O.C.

CMP - CONSUMABLES

• 11K "Investigations of Variability in CMP Slurry Quality and Its Impact on Planarization Process" by P. Hecker; TEXAS INSTRUMENTS; Dallas, TX; and A. Misra and B. Schmidt; AIR LIQUIDE; Dallas, TX.

• 11L "The Effect of Slurry Viscosity on the CMP Process" by B. Mullany and G. Byrne; UNIV COLLEGE; Dublin, IRELAND. (Invited Paper)

  11M "A Study of Effects of Polishing Particle Distribution on Surface Characteristics" by S.C. Lin and M.L. Wu; TSING-HUA UNIV; Taiwan, R.O.C.

• 11N "Recent Advances in CMP Slurry Management Systems" by J. Bare; BOC EDWARDS; Hockessin, DE. (Invited Papers)
  --- POSTER PAPERS ---

• 11O "Thickness Measurements on Patterned Sites for CMP" by D. Scheiner, A. Ravid; NOVA MEASURING; Rehovoth, ISRAEL; and N. Ben-Moshe, E. Bransky; NOVA MEASURING; Phoenix. AZ.

• 11P "Innovative CMP Polishing Belt Development and Char-acterization" by C.S.Xu, E. Zhao; LAM RES; Fremont, CA and B. Lombardo; MADISON CMP; Salem, NH.

• 11Q "The Effects of the Slurry Types on STI Polishing Process" by L. Peng, J.F. Wang and C. Yi; PROMOS TECH; Taiwan, R.O.C.

• 11R "Behavior of CMP Slurry Properties in Continuous Blending and Distribution Systems" by R.K. Singh, B.R. Roberts; BOC EDWARDS; Santa Clara, CA.

• 11S "STI CMP Defect Reduction With Slurry Filtration" by A.H. Liu, R. Solis, J. Li, P. Person, G. Griffith, G. Sprayberry, K. Murray, J. Guzman and N. White; PHILIPS SEMI; Albuquerque, NM; and G. Vasilopoulos, Z. Lin and R. Blum; MILLIPORE; Bedford, MA.

• 11T "CMP Wastewater Treatment" by J.H. Golden; MICRO-BAR; Sunnyvale, CA.

2000 VMIC CONFERENCE EXECUTIVE COMMITTEE

Thomas E. Wade
University of South Florida

Robert S. Blewer	               Shouso Singubara

       Sandia Nat'l Labs                   Hiroshima Univ., Japan

Armin Kohlase                          Joe W. McPherson

       Siemens, W. Germany                 Texas Instruments

Terry O. Herndon	               Dipankar Pramanik

       M.I.T. Lincoln Labs                 VLSI Technology

Loren W. Linholm	               Arjun N. Saxena

       Natl. Inst. Std. & Tech.            Rensselaer Polytech, Ret.

Rob Wolters		               Dirk Tobben

       Philips Res.,Netherlands            Siemens SMD, Germany

Philip J. Fleming	               Martin B. Small

       Appli. Unlimited                    IBM Watson Res., Ret.

Bernd Hofflinger	               C.J. Werkhoven

       Micro.Inst., W. Germany             ASM,The Netherlands

Plan to put your poster up on Tuesday, September 7, before 12:30 pm at the location designated (Salon 1 - 4). Poster boards will be provided as indicated in author kits. Be available to answer questions from 1 - 3 pm on Wed., June 28.

Plan to remove your poster on Wednesday afternoon from 3 - 5 pm. All posters are to be down for room clean-up by 5 pm on Wednesday, June 28.