SIXTH INTERNATIONAL DIELECTRICS
FOR ULSI MULTILEVEL INTERCONNECTION
CONFERENCE (DUMIC) AND EXHIBITION

Registration and Information

February 28 - 29, 2000

SANTA CLARA MARRIOTT HOTEL
Santa Clara, CA.

DUMIC CONFERENCE OBJECTIVES

To assemble researchers and technical support personnel from Industry, Universities and Government Laboratories from around the globe to address all current and future issues related to DIELECTRICS for on-chip ULSI Multilevel Interconnection applications.

Monday, February 28, 2000

OPENING SESSION - 9 A.M.Welcoming Remarks
Dr. Thomas E. Wade
General Chairman
University of South Florida

SESSION I -- 9:15 A.M.
KEYNOTE ADDRESS: "HEAT TRANSFER IN ADVANCED INTERCONNECT SYSTEMS"
Dr. Kenneth E. Goodson
STANFORD UNIVERSITY, Stanford, California

Coffee Break 9:45 - 10 A.M.

SESSION II - 10 A.M. - 11:50 A.M.
VLSI MULTILEVEL INTERCONNECTION
ORGANIC DIELECTRICS

Chair: Dr. Willi Volksen
IBM ALMADER RES. CTR. San Jose, California

  • 2.A "The Status of Low-k Materials Development" by N. H. Hendricks, ATMI Materials; San Jose, CA. Invited Paper (30 minute presentation).

  • 2.B "Preparation and Characterization of Low-k Silica Film Incorporated With Methylene Group" by S. Sugahara, K. Usami and M. Matsumura; TOKYO INST. of TECH; Tokyo, JAPAN; and T. Kadoya and T. Hattori; MASASHI INST. of TECH; Tokyo, JAPAN.

  • 2.C "Gas Ionized Cluster Beam Etching of Fluoro-Polymer Dielectrics" by J. F. McDonald; RENSSELAER POLY-TECH. INST.; Troy, New York .

  • 2.D "Etching Rate Selectivity Improvement Using a Novel Anti-Reflective Coating With DUV Photoresist" by K. Linliu, M.R. Kuo and S. C. Lin; WORLDWIDE SEMI. MFG. CORP; Taiwan, R. O. C.
  • 2.E "A Novel E-Beam Treatment Technique to Improve TaN Barrier Properties for Dual Damascene Cu and Low-k Integration" by C.L. Chang, S. D. Lee and H.W Chiou; ERSO/ITRI; Taiwan, R. O. C.

SESSION IIA - 11:50 A.M. - 12:30 P.M.
VLSI MULTILEVEL INTERCONNECTION
DEDICATED TIME FOR DUMIC POSTER PAPER, EXHIBITION VIEWING

DUMIC LUNCHEON - 12:30 - 1:35 P.M.
" STRATEGIC & TACTICAL IMPACT OF EARTHQUAKES IN TAIWAN "
Dr. Siva Sivaram
MATRIX SEMICONDUCTOR, Palo Alto, California

SESSION III - 1:35 - 3:25 P.M.
VLSI MULTILEVEL INTERCONNECTION
POROUS DIELECTRICS & NOVEL PROCESSES
Chairman: Dr. Suzette Pangrle
AMD CORP., Sunnyvale, California

POROUS DIELECTRICS

  • 3.A "Characterization of Porous Organosilicates for On-Chip Applications" by W. Volksen, R.D. Miller, T. Megbitang, J.Y Lee, D.Y. Yoon, C. Nguyen, J.L. Hedrick, C. Hawker, P. Rice, M. Toney; IBM ALMADEN RES; San Jose, CA; K. Rodbell; IBM WATSON RES; Yorktown, N.Y.; K. Lynn, M. Petkov and M. Weber; WASHINGTON STATE UNIV; Pullman, WA. - Invited Paper (30 minute presentation).

  • 3.B "Characterization of Porous Silica Developed by Union Chemical Laboratories" by L. M. Chen, C. J. Wang, Y. T. Chen and T. Y. Lou; UNION CHEMICAL LABS; ITRS; Taiwan, R. O. C.

  • 3.C "Characterizations of Low Density Porous Material" by H. Arao, M. Egami, A. Nakashima and M. Komatsu; CATALYSTS & CHEMICAL IND. CO; Kitakyushi-shi, JAPAN.
-- POSTER PAPERS --
  • 3.D "A Novel Integration Process of Multi-Step High Density Plasma CVD Process for Air Gap Structures of ULSI Interconnection" by G. Chao and J. Lee; PROMOS TECH; Taiwan, R. O. C.

  • 3.E "Spin-On Properties of Porous Silica" by C. J. Wang, Y. T. Chen and L. M. Chen; UNION CHEMICAL LABS; ITRI; Taiwan, R. O. C.
NOVEL DIELECTRIC PROCESSES
  • 3.F "Design Methodology of Hard Mask Deposition for Organic Low Dielectric Constant Films" by H. W. Chiou, J. H. Tsai, Y. S. Jean and C. Hsia; ERSO/ITRI; Taiwan, R.O.C.

  • 3.G "The Effect of Channel Doping on the Hot-Electron Resistance of n-MOSFETs With Gate Oxide Grown on Nitrogen Implanted Si Substrates" by Y. L. Wu; NAT'L CHI-NAN UNIV; Taiwan, R.O.C.; J. J. Chang and T. E. Hsieh; NAT'L CHIAO-TUNG UNIV; Taiwan, R.O.C.; and J.L. Tray; NAT'L TSING-HUA UNIV; Taiwan, R.O.C.
-- POSTER PAPERS --
  • 3.H "The Effect of Line Box Configuration on Overlay Per-formance" by L. G. Yao, J. J. Shin, J. Lin, S. P. Jeng and M. H. Chi; WORLD SEMI. MFG. CORP.; Taiwan, R.O.C.

Coffee Break 3:25 - 3:40 P.M.

SESSION IV - 3:40 - 5:30 P.M.
VLSI MULTILEVEL INTERCONNECTION
INORGANIC DIELECTRICS - PART I

Chairman: Dr. Neil H. Hendricks
ATMI MATERIALS, San Jose, California

  • 4.A "Void Free Pre-Metal Dielectric Gap-Fill Capability With CVD Films for Sub-Quarter Micron ULSI" by V. Y. Vassiliev; CHARTER SEMI.; SINGAPORE. Invited Paper (30 minute presentation).

  • 4.B "Integration of Advanced APCVD BPTEOS; Ozone Films for Sub-0.15 Micron Generation Chemical Mechanical Polish Poly-Metal-Dielectric Applications" by T. O. Curtis, Z. Yuan, J. Lam and K. Kapkin; SILICON VALLEY GP; Scotts Valley, CA.; and B. Birmingham; SEMATECH; Austin, TX.

  • 4.C "The Effects of Temperature on Florinated-HDP Oxide for Subtractive and Damascene Architectures" by J. Yota; CONEXANT SYS; Newport Beach, CA.; and J. Hander and M. Sanganeria; NOVELLUS SYS; San Jose, CA.

  • 4.D "Inorganic Low-k Materials by Long Residence Plasma CVD Method" by N. Matsuki, A. Matsunoshita, J. S. Lee, Y. Naito and Y. Morisada; ASM JAPAN; Tokyo, JAPAN.

  • 4.E "Preparation and Properties of Fluorinated Amorphous Carbon Films by ECR-CVD Method" by J. H. Ting, F. H. Ko, F. M. Pan, T. G. Tsai, B. T. Dai; NAT'L NANO DEVICE LAB; Taiwan, R.O.C.; and C. C. Chen and T. C. Chu; NAT'L TSING HUA UNIV; Taiwan, R.O.C.
-- POSTER PAPERS --
  • 4.F "Characterization of High Density Plasma CVD Films for Sub-Quarter Micron Devices Application" by C. C. Tsan, Y.L. Wang, Y. L. Cheng, J. K. Lan; TSMC; Taiwan, R.O.C.; and S. Y. Chiou and M. S. Feng; NAT'L CHIAO-TUNG UNIV.; Taiwan, R.O.C.

  • 4.G "Simplified CMP Planarization Process Module for Trench Isolation Applications" by K. Kapkin, M. Mogaard and T. Curtis; SILICON VALLEY GP; Scotts Valley, CA. and C. Artufel; ATMEL; Cedex, FRANCE.

  • 4.H "Gap-Fill Capability of Subatmospheric Pressure Chemically Vapor Deposited TEOS-Ozone Doped Glass Films Annealed at Low Thermal Budget Conditions" by V. Y. Vassiliev, C.Y. Wang, J. L. Sudijono and A. Cuthbertson; CHARTER SEMI. MFG.; SINGAPORE; and T. Chu, P.C. Tan, Y. S. Heng and G. Zou; APPLIED MATERIALS; South-East ASIA; and A. Bhatnagar, R. Pan and P. Gee; APPLIED MATERIALS; Santa Clara, CA.

Tuesday, February 29, 2000

SESSION V - 8:30 - 9:50 A.M.
VLSI MULTILEVEL INTERCONNECTION
ANTI-REFLECTIVE COATING APPLICATIONS

Chairman: Dr. Philip J. Fleming
PHILIP J. FLEMING & ASSOC., Colorado Springs, CO.

  • 5.A "A Novel Plasma Treatment Method to Improve DUV Photoresist Footing on Inorganic Anti-Reflective Layer (ARL)" by S. D. Lee, C. M. Wang, C. I. Chang, S. Y. Chou, H. W. Chiou and C. Hsia; ERSO/ITRI; Taiwan, R.O.C.

  • 5.B "Application of Hydro-Silicon Oxynitride Films as Anti-Reflective Layer for Sub-0.18 Micron Lithography Process" by W. K. Cheng, Y. L. Wang, S. A. Wu, J. Dun, S.Y. Chiu and M.S. Feng; TSMC; Taiwan, R.O.C.

  • 5.C "A Study of Batchtype System (N2O Treatment or Cap Oxide) For Plasma-Enhanced CVD SiOxNy as Anti-Reflective Coating" by D. H. Lee, G. S. Cho, Y. M. Kwon, J. B. Jang, R. S. Kim, C. G. Lee, S. R. Beck, G. O. Park, H. S. Ko, S. H. Kim; ANAM SEMI.; Kyungii-do, KOREA.

  • 5.D "Integration of PECVD SiOxNy as Anti-Reflective Coating for Fabrication of DRAM Storage Node Contact" by Y. L. Tu, Y. H. Liu, T. C. Yu and G. Cheng; WSMC; Taiwan, R.O.C.

Coffee Break 9:50 - 10:05 A.M.

SESSION VI - 10:05 A.M. - 12:00 P.M.
VLSI MULTILEVEL INTERCONNECTION
INORGANIC DIELECTRICS - Part II

Chairman: Dr. Carlye Case
ATT BELL LABS/LUCENT TECH.
Murry Hill, New Jersey

  • 6.A "Fluorine Diffusion in Fluorine-Doped Silicon Dioxide" by R. Wistrom, G. Bomberger, M. Lavoie and J. Gambino; IBM MICRO; Essex Junction, VT.

  • 6.B "Sub-100 nm Damascene Metal Gate Transistors with Ultra-Thin (1.5 nm) Ta2O5 Gate Insulator" by A. Yagishita, T. Saito, K. Nakajima, S. Inumiya, K. Matsuo, Y. Akasaka, Y. Ozawa, H. Yano, G. Minamihaba, Y. Matsui, Y. Tsunashima, K. Suguro, T. Arikado and K. Okumura; TOSHIBA CORP; Yokohama, JAPAN. - Invited Paper (30 minute presentation)

  • 6.C "Plasma Treatment of Low-k Flowfill Films" by K. Beekmann, A. Wilby, S. McClatchie and J. Macneil; TRIKON TECH; Newport, WALES; W. J. Hsia; LSI LOGIC; Santa Clara, CA.

  • 6.D "Properties of Subatmospheric Pressure Borophosphosilicate Glass Films Annealed at Low Thermal Budget Conditions" by C. Wang, V. Vassiliev, K. W. Tan and J. L. Sudijono; CHARTER SEMI. MFG.; SINGAPORE.

  • 6.E "Characterization and Evaluation of Low-k Dielectrics for ULSI Multilevel Interconnection" by H. G. Huang, Y. H. Hsieh, S.L. Chou, J. S. Wen and J. J. Hsu; WINBOND ELEC; Taiwan, R.O.C.
-- POSTER PAPERS --
  • 6.F "Study of Rapid Thermal Chemical Vapor Deposition Silicon Nitride" by A. T. Cheong, L. S. Yee, O. P. Ing and J. Sudijono; CHARTER SEMI. MFG.; SINGAPORE.

  • 6.G "Impact of STI Oxide Elevation on Junction Leakage and Narrow Active Sheet Resistance" by Y. Quah, K.H. Lee, L. Lim, H. B. Chua, H. L. Yap and E. Z. Liu; CHARTER SEMI. MFG.; SINGAPORE.

SESSION VII
VLSI MULTILEVEL INTERCONNECTION
DIELECTRIC RELIABILITY ISSUES

- POSTER PAPERS -

  • 7.A "Improvement of Via Reliability by Post SOG Etch Back Treatment" by S.C. Tseng, M. J. Liu, H. G. Huang, L. J. Liu, J.S. Wen, J. J. Hsu; WINBOND ELEC; Taiwan, R.O.C.

  • 7.B "Anti-Corrosion Using Polymer Etch and Cl2 Replacement Method" by Y.K. Hwang, C.D. Young, K.J. Chang, S.F. Chen and K. W. Huang; TSMC; Taiwan, R.O.C.

  • 7.C "Plasma Induced Wafer Surface Voltage and Its Electrochemical Corrosion in Tungsten Plug Process" by C.J. Wang, C. Lin, B. T. Lin, K. Y. Y. Doong and M. Chen; WORLDWIDE SEMI. MFG.; Taiwan, R.O.C.; and A. Chou; APPLIED MAT'L; Taiwan, R.O.C.

  • 7.D "A Method to Improve Adhesion Property Between Organic Low-k Material and Inorganic CVD Hardmask" by S.D. Lee, C. I. Chang, J. H. Tsai and H.W. Chiou; ERSO/ITRI; Taiwan, R.O.C.

NOTICE TO AUTHORS OF POSTER PAPERS: Put up posters on Monday, Feb. 28, before 9 AM at the location designated (Salon 1 - 4). Be available to answer questions during Session IV. Remove posters by 4 PM.