FIFTH INTERNATIONAL
CHEMICAL-MECHANICAL POLISH (C.M.P.)
PLANARIZATION FOR ULSI MULTILEVEL INTERCONNECTION
CONFERENCE (CMP-MIC) AND EXHIBITION

Registration and Information

March 2 - 3, 2000

SANTA CLARA MARRIOTT HOTEL: Santa Clara, CA.

CMP-MIC CONFERENCE OBJECTIVES

To assemble researchers and technical support personnel from Industry, Universities and Government Laboratories from around the globe to address all current and future issues related to CHEMICAL-MECHANICAL POLISH PLANARIZATION as applied to on-chip ULSI Multi-level Interconnection applications.

Thursday, March 2, 2000

OPENING SESSION - 8:00 A.M.
Welcoming Remarks
Dr. Thomas E. Wade
General Chairman: University of South Florida

SESSION I -- 8:15 A.M.
KEYNOTE ADDRESS
CMP CORPORATE OFFICERS: " OUR COMPANY'S VISION FOR CMP IN THE FUTURE "
Richard J. Faubert, President and CEO, SPEEDFAM-IPEC
Jim Burke, CEO, R. HOWARD STRASBAUGH
Chris Smith, Corp. VP, APPLIED MATERIALS
James W. Bagley, Chairman & CEO, LAM RESEARCH CORP
John Aldeborgh, President EBARA CORP

FOLLOWED BY QUESTION & ANSWER SESSION:
Moderator: Michael A. Martinez, MCA Corp.


Coffee Break 9:45 - 10 A.M.

SESSION II - 10 A.M. - 12 Noon VLSI MULTILEVEL INTERCONNECTION
C.M.P. CONDUCTOR PROCESSES - Part I
Chairman: Dr. Duane Boning
MASS. INST. of TECH. (MIT), Cambridge, Massachussetts

  • 2.A "Kinetics of Different Polisher Platforms and Challenges of Copper CMP" by K. Yang; ADVANCED MICRO DEVICES; Sunnyvale, CA. Invited Paper

  • 2.B "CMP Processes for Noble Metals and Noble Metal Oxides" by G. Beitel, R. F. Schnabel, G. Mainka, A. Sanger and C. Dehm; INFINEON TECH; Munich, GERMANY; and R. Small and Z. Chen; EKC TECH; Hayward, CA.

  • 2.C "Role of Alumina Phase and Size in Tungsten CMP" by D. Stein; SANDIA NAT'L LABS; Albuquerque, NM; and B. Her; FERRO; Penn Yan, N.Y.

  • 2.D "Fundamental Mechanisms in Metal CMP Using Model Slurries" by B. C. Lee, B. Wang, D. J. Duquette and R. J. Gutmann; RENSSELAER POLYTECH; Troy, N.Y. Invited Paper

  • 2.E "Chemical Mechanical Planarization of Copper Interconnects Using Fixed Abrasive Polishing Pad" by V. Koinkar, R. Golzarian, Q. Luo, M. VanHanehem, J. Shen and P. Burke; RODEL; Newark, DE; and T. Fletcher, L.C. Hardy, J. Kollodge, J. Trice, T. Engfer and E. Funkenbusch; 3M CORP; St. Paul, MN.

  • 2.F "Hydroxyl Radical Formation and Copper Line Corrosion in Cu-CMP" by J. Keleher, E. Tyre, S.V. Babu and Y. Li; CLARKSON UNIV; Potsdam, N.Y.; and R. Her; FERRO; Penn Yan, N.Y.

--- POSTER PAPERS ---

  • 2.G "Influence of Erosion and Dishing During Cu-CMP on Electrical Performance" by J. Grillaert, E. Vrancken, W. Fyen, M. Meuris and M. Heyns; IMEC; Kapeldreef, BELGIUM.

  • 2.H "Separation of Pad and Slurry Effects in Copper CMP" by D.R. Evans; SHARP LABS; Camas, WA; and M.R. Oliver and M.K. Ingram; RODEL; Newark, DE.

  • 2.I "Tungsten CMP Evaluation of Politex/IC1000 Pads Using Fe(NO3)3H2O2 Based Slurries With Oxide Buffing & Process Performance Optimization for 0.25 Micron Device Process" by P.K. Niu, S.N. Lee, S.M. Tseng; WSMC; Taiwan, R.O.C.

  • 2.J "Copper CMP: The Role of Barrier Material and Its Effect on The Number of Polishing Steps" by D.A. Hansen, G. Moloney, M.E. Witty; MULTI PLANAR TECH; San Jose, CA.

  • 2.K "Robust Process Performance Window of Tungsten Chemical Mechanical Polish" by S.Y. Shih, L.H. Kuo, H.W. Chiou, Z.H. Lin and C. Hsia; ERSO/ITRI; Taiwan, R.O.C.

Box Lunches - 12:00 to 12:35 P.M.

Visit Industrial Exhibitors 12:35 - 1:15 PM


SESSION III - 1:15 - 2:55 P.M.
VLSI MULTILEVEL INTERCONNECTION
C.M.P. PROCESS CHARACTERIZATION
Chairman: Dr. Dale Hetherington
SANDIA NATIONAL LABS, Albuquerque, New Mexico

  • 3.A "Integration of CMP Into a Low Volume, Fast Cycle Time 0.35 Micron CMOS ASIC Manufacturing Line" by K. Stribley, G. Hayward, M. Putt and D. Inman; MITEL SEMI; Plymouth, UNITED KINGDOM. Invited Paper

  • 3.B "Evolution of CMP Process Control Methodology for High Volume Manufacturing" by J. A. McKinnis, S.L. Lantz and D. E. Sauer; INTER CORP; Hillsboro, OR.

  • 3.C "Production Status of 300mm CMP" by K. Ebner, P. Faustmann, W. Glashauser, D. Haggart and L. Teichgraber; INFINEON SC300; Dresden, GERMANY.

  • 3.D "Advanced Front End CMP and Integration Solutions" by R. Jin and G. Amico; APPLIED MATERIALS; Santa Clara, CA. Invited Paper

  • 3.E "A Viable 300 mm Copper CMP Process" by J. Mendonca, F. Hampton and D. Keenan; MOTOROLA; Austin, TX; and A. Zutshi, D. Vijay, B. Withers, S. Huey, R. Bajaj, R. Tolles and F. Redekar; APPLIED MAT'L; Santa Clara, CA.

Coffee Break 2:55 - 3:10 P.M.

SESSION IV - 3:10 - 5:30 P.M.
VLSI MULTILEVEL INTERCONNECTION
C.M.P. SHALLOW TRENCH ISOLATION (STI)
Chairman: Dr. Peter Burke
RODEL INC, Newark, Delaware

  • 4.A "Reverse Active Mask and CMP Over Polishing Impact on Shallow Trench Isolation for a 0.20 Micron Flash Memory" by P. Colpani, S. Ratti, A. Rebora and D. Berselli; ST MICRO; Agrate Brianza, ITALY. Invited Paper

  • 4.B "Effects of a CMP Process on Within-Wafer STI Planarity" by Y. Wu, G. Brooks, T. Chamberlin and M. Lube; IBM MICRO; Essex Junction, VT.

  • 4.C "Ceria-Based Slurries for STI Planarization" by S.V. Babu and R. Mackay; CLARKSON UNIV; Potsdam, N.Y.; B. America; KODAK; and R. Srinivasan and Y.S. Her; FERRO; Penn Yan, N.Y. Invited Paper

  • 4.D "Integration of STI Reverse Mask Effect and 520C Ozone-TEOS Based Oxide Film on STI CMP Process for the Sub-0.15 Micron DRAM" by T.H. Lee, W.P. Chang, T.C. Lin, H. L. Meng, J. S. Jeng, C. L. Kuo, K.C. Lin and S.C. Chien; UNITED MICRO CORP; Taiwan, R.O.C.

  • 4.E "The Effects of Slurries With Pattern Size and Step Height in Shallow Trench Isolation Chemical Mechanical Polishing" by S.I. Lee, C.I. Kim, H. Kim, J.H. Kim, C.W. Nam, S. Kim and C.T. Kim; HYUNDAI; Kyoungki-do, KOREA.

  • 4.F "Design and Processing Considerations in a Production Worthy Shallow Trench Isolation Process" by R. Sehgal, S. Chadda, L. Prowell and G. Frazier; ATMEL CORP; Colorado Springs, CO. Invited Paper

  • 4.G "Dishing Reduction for STI-CMP by Inserting Poly Buffer Layer" by V.S.K. Lim and W.L. Goh; NANYANG TECH UNIV; SINGAPORE; and F. Chen, A. See, C.H. Loh, C. Lin, Q.H. Zhong and M. Xin; CHARTER SEMI; SINGAPORE.

--- POSTER PAPERS ---

  • 4.H "Monitoring of Chemical-Mechanical Polishing Quality in Shallow Trench Isolation" by H.C. Chen, Y.T. Wei, M.S. Yang and V. Wang; UNITED MICRO CORP; Taiwan, R.O.C.

  • 4.I "Effects of Pattern Density and Pitch on the STI CMP Process" by H.H. Lu, L.M. Chen, C.K. Min and Y.T. Chen; UNION CHEM LAB, ITRI; Taiwan, R.O.C.


Friday , March 3, 2000

SESSION V - 8:00 - 9:40 A.M.
VLSI MULTILEVEL INTERCONNECTION
CMP MODELING & SIMULATION
Chairman: Dr. Bin Zhao
CONEXANT SYSTEMS, Newport Beach, California

  • 5.A "Overview of Methods for Characterization of Pattern Dependencies in Copper CMP" by T. Park, T. Tugbawa and D. Boning; MASS. INST. of TECH; Cambridge, MA. Invited Paper

  • 5.B "The Mechanical Behavior and Modeling of Polyurethane CMP Pads" by H. Liang, J. Lee and J. Oung; UNIV of ALASKA; Fairbanks, ALASKA. Invited Paper

  • 5.C "Gradient and Radial Uniformity Control of a CMP Process Utilizing a Pre- and Post- Measurement Strategy" by J. Moyne, C.E. Chemali and J. Kim; UNIV MICHIGAN; Ann Arbor, MI; and T. Parikh; SEMATECH; Austin, TX; and J. Chapple, J. Colt, R. Nadeau and P.Smith; IBM MICRO; Essex Junction, VT.

  • 5.D "Finite Element Analysis and Measurement of CMP Pad Displacement" by J.A. Tichy, C.J. Clutz and T.S. Cale; RENSSELAER POLYTECH; Troy, N.Y. Invited Paper

  • 5.E "Characterization of Endpoint and Wafer Level Non-Uniformity Using In-Situ Thermography" by D. White, D. Boning, A. Gower; MASS INST of TECH; Cambridge, MA.

--- POSTER PAPERS ---

  • 5.F "A Plasticity Based Model for Material Removal During Chemical Mechanical Polishing" by A. Chandra and G. Fu; IOWA STATE UNIV; Ames, IA; S. Guha; SPEEDFAM-IPEC; Chandler, AZ; and G. Subhash; MICHIGAN TECH UNIV; Houghton, MI.

  • 5.G "Oxide Polishing Kinetics, Physical Based Modeling" by V. Sukharev and J. Pallinti, LSI LOGIC; Santa Clara, CA.

  • 5.H "The Effects of Wafer Edge Contact Stress on the Removal Rate Non-Uniformity During Chemical-Mechanical Polishing Process" by C.C. He, C.Y. Chiou and W. C. Pan; CHUNG-SHAH INST of SCI & TECH; Taiwan, R.O.C.

  • 5.I "Empirical Modeling for CMP Removal Rate Profile Control and Optimization" by A. Jensen, J. Farber and P. Renteln; LAM RES CORP; San Jose, CA.

  • 5.J "Using Smart Dummy Fill and Selective Reverse Etchback for Pattern Density Equalization" by B. Lee, D. Boning; MIT; Cambridge, MA; and D. Hetherington and D. J. Stein; SANDIA NAT'L LABS; Albuquerque, NM.

  • 5.K "A New Model by Product Effective Polish Rate for Oxide CMP APC System" by J. Y. Lin; UNITED MICRO CORP; Taiwan, R.O.C.

Coffee Break 9:40 - 9:50 A.M.

SESSION VI - 9:50 - 11:30 A.M.
VLSI MULTILEVEL INTERCONNECTION
CMP COMSUMABLES
Chairman: Dr. Frank B. Kaufman
CABOT CORP., Aurora, Illinois

  • 6.A "STI CMP Using Fixed Abrasive - Demands, Measurement Methods and Results" by A. Romer, P. Thieme and M. Hollatz; INFINEON; Dresden, GERMANY; and T. Donohue; APPLIED MATERIALS; Santa Clara, CA; and J. Gagliardi; 3M LABS; Dresden, GERMANY. Invited Paper

  • 6.B "Viscoelastic Behavior of Polishing Pad and Its Influence on Polishing Non-Uniformity" by H.J. Kim, H. Y. Kim and H. D. Jeong; PUSAN UNIV; Pusan, SOUTH KOREA.

  • 6.C "Treatment of CMP Waste" by S. Raghavan; UNIV ARIZONA; Tucson, AZ. Invited Paper

  • 6.D "Pad Life Optimization by Characterization of a Fund-amental Pad-Disk Interaction Property" by G. Prabhu, S. Kumaraswamy and D. Flynn; APPLIED MAT'L; Santa Clara, CA; and S. Qamar and T. Namola; ABRASIVE TECH; Westerville, OH.

  • 6.E "4th Generation W Slurry for Plug and Damascene Applications" by M Peterson, B. Tredinnick and R. Small; EKC TECH; Hayward, CA. Invited Paper

    --- POSTER PAPERS ---

  • 6.F "Correlating Slurry Film Thickness and Friction Between Wafer and Pad During Oxide CMP" by M. Moinpour and A. Philipossian; INTEL CORP.; Santa Clara, CA; J. Lu, J. Coppeta, C. Rogers and V. Manno; TUFTS UNIV; Bedford, MA; and F. Kaufman; CABOT; Aurora, IL.

  • 6.G "CMP Wastewater Treatment" by J.H. Golden; MICRO-BAR; Sunnyvale, CA.

  • 6.H "Pad Surface Roughness After Conditioning in CMP" by C.T. Wang, W. Jeng and C.C. Liang; ASIA IC MIC; Taiwan, R.O.C.; L.K. Chou and R. Chen; WINBOND; Taiwan, R.O.C.

  • 6.I "CMP of TaSiN Barrier for Stack Capacitors" by L. Economikos and F. F. Jamin; IBM/INFINEON ALLIANCE; Hopewell Jct., N.Y.

  • 6.J "A Novel Disk Technology and Performance for W CMP Pad Conditioning" by T.C. Wang, T.E. Hsieh; NAT'L CHIAO-TUNG UNIV; Taiwan, R.O.C.; Y.L. Wang; TAIWAN SEMI; Taiwan, R.O.C.; K. Yang, W. Pan; APPLIED MAT'L; Taiwan, R.O.C.; and J. Sung; KINIK CO; Taiwan, R.O.C.

  • 6.K "Point-of-Use Filtration Lifetime for CMP Slurries" by C. Lee; CABOT; Aurora, IL.

  • 6.L "Fundamentals of Gas Phase Production of Fumed Metal Oxides" by H. Muehlenweg, F. Klaessig, W. Lortz, G. Varga and A. Gutsch; DEGUSSA-HUELS; Piscataway, N.J.

  • 6.M "Diagnostic and Prediction of Pad Life in CMP" by C.T. Wang, W. Jeng; ASIA IC; Taiwan, R.O.C.; and C.Y. Huang, Y.Y. Chan; WINBOND; Taiwan, R.O.C.

  • 6.N "Bond Strength and Crystal Retention Properties of CMP Pad Conditioners Manufactured With P.B.S. Brazed Crystal Bonding Electroplated Crystal Bonding Technologies" by K. Bailey and S. Qamar; ABRASIVE TECH; Westerville, OH.

  • 6.O "Defect Evaluation for Fixed Abrasive CMP" by K. Mikhaylich and M. Ravkin; LAM RES; Fremont, CA.

  • 6.P "Enhancement of Padlife on Orbital Tools Through Uniform Pad Conditioning" by D. Potter and I. Golkar; SPEEDFAM-IPEC; Chandler, AZ.

SESSION VII - 11:30 A.M. - 12:30 P.M.
VLSI MULTILEVEL INTERCONNECTION

DEDICATED TIME FOR C.M.P. POSTER PAPERS, EXHIBIT VIEWING


CMP-MIC LUNCHEON - 12:30 - 1:45 P.M.

" FLOW VISUALIZATION & FLUID DYNAMICS MEASUREMENTS DURING CMP PROCESS "

Drs. Ara Philipossian & Mansour Moinpour
INTEL CORP., Santa Clara, California


SESSION VIII - 1:45 - 3:25 P.M.
VLSI MULTILEVEL INTERCONNECTION
C.M.P. DIELECTRIC PROCESSES
Chairman: Dr. Paul Feeney
CABOT CO., Aurora, Illinois

  • 8.A "Oxide CMP: Planarization Performance Upon Different Integration Schemes" by E. Perrin, M. Rivoire, A. Inard, M. Jouty, A. Fleury and H. Jaouen; S T MICRO; Crolles, FRANCE; J. Van Hassel; PHILIPS; J.C. Oberlin; CNET; Meylan, FRANCE. Invited Paper

  • 8.B "Improving Within-Die Nonuniformity in Dielectric CMP" by T. Smith; SKW; Fremont, CA; S. Fang, G. Shinn, J. Stefani, Z. Tang, S. Chang, S. Garza and J. Campbell; TEXAS INSTRUMENTS; Dallas, TX; D. Boning; MIT; Cambridge, MA.

  • 8.C "CMP of Various Low-k Dielectric Materials in Copper Dual-Damascene and Subtractive Aluminum Applications" by F. Zhang and P. Galvez; ALLIED SIGNAL; Sunnyvale, CA.

  • 8.D "Total Planarization of the MIT 961 Mask Set Wafers Coated With HDP Oxide for STI CMP Using Fixed Abrasives" by J.J. Gagliardi; 3M CO; St. Paul, MN.; and T. Vo; RODEL; Sunnyvale, CA. Invited Paper

  • 8.E "The CMP Process of Polyimide for Low-k Dielectric Application in ULSI Multilevel Interconnection" by Y.L. Tai and Y.L. Wang; TSMC; Taiwan, R.O.C.

--- POSTER PAPERS ---

  • 8.F "FSG-CMP Process Development & Characterization for 0.18 Micron Technology & Beyond" by L.S. Leong, F. Chen, F.L. Chin, C. H. Loh, C. Lin and A. Cuthbertson; CHARTER SEMI MFG; SINGAPORE; V. Lim; NANYANG TECH UNIV; and D. Lim; NAT'L UNIV of SINGAPORE; SINGAPORE.

  • 8.G "Defect Reduction for ILD CMP" by P. Feeney; CABOT; Aurora, IL.

  • 8.H "Investigation of Via Chain Resistance in IMD (HDP-CVD/PE-CVD) Planarization by CMP" by J.H. Kim, H. Kim, S.I. Lee, C.W. Nam, S.B. Kim and C.T. Kim; HYUNDAI; Kyungki-do, KOREA.

  • 8.I "Optimizing Dielectric CMP Planarization Processes" by D.L. Hetherington, D.J. Stein; SANDIA LABS, Albuquerque, NM.

  • 8.J "Characterization of an Oxide CMP Polishing System Containing an Independently Controlled Guide Ring" by K.G. Pierce, R. Sehgal, S. Chadda; ATMEL; Colorado Springs, CO.

  • 8.K "Developments in Dielectric & Metal CMP Processes and Control Capabilities of Orbital Technology for Enhanced ILD Processes" by S. Guha, F. Elkhodr, D. Roehl, R. Ross, F. O'Moore, M. Ferra, P. Parikh and F. Krupa; SPEEDFAM-IPEC; Chandler, AZ.

  • 8.L "Characterizing an ILD CMP Process Using Colloidal Silica Slurry to Achieve a Longer Pad Life" by P. Chavez; INTEGRATED DEVICE TECH; Salinas, CA; and A. J. Clark; RODEL; Phoenix, AZ.

  • 8.M "Optimization of Polishing Pad Profile and Its Effect on 300 mm Oxide CMP Process" by H.M. Wang, G. Moloney and S. DeGuzman; MULTI PLANAR TECH; San Jose, CA.

SESSION IX - 3:25 - 4:45 P.M.
VLSI MULTILEVEL INTERCONNECTION
C.M.P. NOVEL APPLICATIONS
Chairman: Dr. Michael A. Fury
SILTERRA SDN., Kulim, Malaysia

  • 9.A "A Novel High-Frequency Quasi-SOI Power MOSFET Using a CMP Technology" by A. Matsumoto, Y. Hiraoka, T. Sakai and T. Yachi; NTT RES. LABS; Tokyo, JAPAN. Invited Paper

  • 9.B "Chemical Mechanical Planarization of Thin Film Read/ Write Heads" by E. Lee, F. Martin, F. Eschbach, J. Ortega, B. Phipps; IBM Almadan Res. Ctr; San Jose, CA. Invited Paper

  • 9.C "Atomically Flat Surface of Compound Semiconductors by Chemical-Mechanical Polishing" by P.S. Dutta and R.J. Gutmann; RENSSELAER POLYTECH INST; Troy, N.Y. Invited Paper

  • 9.D "Applications of CMP in the Thin Film Magnetic Head Fabrication" by D.S. Zhou; READ-RITE CORP; Fremont, CA. Invited Paper

SESSION X - 4:45 - 6:00 P.M.
VLSI MULTILEVEL INTERCONNECTION
C.M.P. CONDUCTOR SYSTEM - Part II
Chairman: Dr. Kathleen Perry
OBSIDIAN INC Fremont, California

  • 10.A "Annealed Properties of Electroplated Cu Thin Film and Their Effect on CMP" by I. Ivanov and C.H. Ting; CUTEK RES; San Jose, CA. Invited Paper

  • 10.B "Investigation of Aluminum CMP to Apply to Sub-Quarter Micron DRAM Devices" by J.Y. Kim, C.H. Jeong, N.H. Park, S.B. Han, J. W. Park; HYUNDAI; Cheongju, KOREA; and J. J. Kim; SEOUL NAT'L UNIV; Seoul, KOREA.

  • 10.C "Unlocking Copper Damascene Puzzle" by K. Wijekoon; APPLIED MATERIALS; Santa Clara, CA. - Invited Paper

  • 10.D "Advances in Chemical Mechanical Polishing of Cu Inter-connects" by S. Wang, V. Brusic, J. Hawkins, I. Cherian, L. Knowles, C. Schmidt, B. Cruz, K. Miller, D. Garcia, H. Chou, C. Baker, G. Grover and C. Yu; CABOT; Aurora, IL.

-- POSTER PAPERS --

  • 10.E "Dual Damascene Tungsten Process for the Bit Line Appli-cation of DRAMs" by Y.A. Cho, W.H. Jin, W.J. Lee and J. Hong; HYUNDAI; Cheongju, KOREA; and S.K. Rha; TAEJON NAT'L UNIV; Taejon, KOREA.

  • 10.F "IR Thermal Mapping of Process Variations at Cu-CMP" by Z.H. Lin, H.W. Chiou, S.Y. Shih and C. Hsia; ERSO/ ITRI; Taiwan, R.O.C.

  • 10.G "Integration Methodology of W CMP Process for Sub- 0.18 Micron Process Applications" by Y.L. Wang, J. Wu, T.C. Wang, J.K. Lan, Y.L. Cheng and J. Dun; TSMC; Taiwan, R.O.C.

  • 10.H "Polish Behavior of Tungsten Plug Planarization" by Z.H. Lin, H.W. Chiou, S.Y. Shih and C. Hsia; ERSO/ITRI; Taiwan, R.O.C.

SESSION XI
VLSI MULTILEVEL INTERCONNECTION
C.M.P. CLEANING PROCESSES

- POSTER PAPERS -

  • 11.A "Discussion of Various CMP Scratch Issues" by E. Tseng, M. Meng and S.C. Peng; UNITED MICRO CORP; Taiwan, R.O.C.

  • 11.B "Particle Adhesion Mechanisms in Oxide and Copper CMP and Post-CMP Cleaning" by A. Busnaina; CLARKSON UNIV; Potsdam, N.Y.; F. Zhang; ALLIED SIGNAL; Sunnyvale, CA.

  • 11.C "Cleaning, Rinsing and Drying Effects in Post-Cu CMP Clean" by W. Fyen, R. Vos, I. Teerllinck, E. Vrancken, J. Grillaert, M. Meuris, M. Heyns; IMEC; Heverlee, BELGIUM.

  • 11.D "The Study of Slurry Residue Issue in CMP Process" by K.J. Chen, H.B. Lu and P.W. Yen; UNITED MICRO CORP; Taiwan, R.O.C.

  • 11.E "Advanced Post CMP Cleaning With Single Wafer Immer-sion Megasonic in a Next Generation Dry-in Dry-out CMP System" by J. Tang, B. Fishkin, A. Lerner, M. Sugerman, F. Redeker, B.J. Brown; APPLIED MAT'L; Santa Clara, CA.

  • 11.F "Low Cost Post Tungsten CMP Treatment" by B.T. Lin, P.K. Nil, K.H. Wang; WSMC; Taiwan, R.O.C.

  • 11.G "Copper CMP: Paradyne Shift in Responsibility" by D.A. Hansen, G. Moloney and A. Reyes; MULTI PLANAR TECH; San Jose, CA.

  • 11.H "Post-CMP Cleaning: Scrub, Megasonic or Scrub/Meg Combination??" by M. Olensen and B. Fraser; VERTEQ; Santa Ana, CA.

SESSION XII
VLSI MULTILEVEL INTERCONNECTION
C.M.P. INSTRUMENTATION & HARDWARE

- POSTER PAPERS -

  • 12.A "Non-Contact Metrology for Characterization of Copper CMP" by M. Banet, M. Joffe, M. Gostein, A. Maznev, C. Moore and R. Sacco; PHILIPS ANALYTICAL; Natick, MA.

  • 12.B "Improvement of Chemical Mechanical Polishing Characteristics By Using Nozzle Type Injector" by K.J. Kim, S.T. Moon and H.D. Jeong; PUSAN UNIV; Pusan, KOREA.

  • 12.C "Automatic Analysis and Control of Hydrogen Peroxide for Copper and Tungsten Polishing CMP Slurry" by K. Nicholes, T. Lemke, J. Bare, B. Johl; BOC EDWARDS; Santa Clara, CA.

  • 12.D "Advanced In-Line Monitoring of Metal Residual and Dielectric Loss at Cu-CMP" by Z.H. Lin, H. W. Chiou, S.Y. Shih and C.Hsia; ERSO/ITRI; Taiwan, R.O.C.

  • 12.E "On-Line Measurement of Oxide Erosion, Metal Residuals and Field Oxide Thinning in Copper CMP Processing" by B. Srinivasan and F. Stanke; SENSYS INST; Santa Clara, CA.

  • 12.F "Investigation of Intelligent CMP for Cu-CMP" by K. Kabayashi, Y. Samitsu, E. yamamoto and K. Tanaka; OKAMOTO MACHINE TOOL; Kanagawa, JAPAN.

  • 12.G "Process Control and Endpoint Detection With In Situ Rate Monitor System in Chemical Mechanical Polishing of Cu Layer" by B.W. Adams, B. Swedek, R. Bajaj, S. Nanjangud, A. Wiswesser, S. Tsai, D.A. Chan, F. Redeker and M. Birang; APPLIED MAT'L; Santa Clara, CA.

  • 12.H "The Study of W CMP Endpoint Detection by Motor Current for Different Glue Layer" by P.K. Niu, S.N. Lee, S.M. Tseng; WSMC; Taiwan, R.O.C.

  • 12.I "An Improvement of Oxide CMP Process Performance Through the Floating Head Design" by H.M. Wang, G. Moloney, M. Stella and S. DeGuzman; MULTI PLANAR TECH; San Jose, CA.

  • 12.J "Comparison of Two Instruments Used for Measuring Concentration of Large Particles (> 1 Micron) in CMP Slurry" by M.R. Litchy, K. Nicholes and D.C. Grant; BOC EDWARDS; Chaska, MN.


NOTICE TO AUTHORS OF POSTER PAPERS

Plan to put your poster up on Friday, March 3, before 9 am at the location designated (Salon 1 - 4). Poster boards will be provided. Be available to answer questions during Session IV. Remove all posters by 4 PM Friday, Mar. 3.